Samsung Foundry formally started to produce chips using its 7LPP (7 nm low power plus) fabrication process last October and has not slowdown development of its manufacturing technologies since then. The company is on track to start mass production using its refined 6LPP (6 nm low power plus) technology in the second half of 2019. In addition, the company said that it would tape out its first 5LPE (5 nm low power early) SoCs and would complete development of its 4LPE (4 nm low power early) process in the coming months too.

Strong Demand for Chips

Because of dropping DRAM and NAND prices, consolidated revenue of Samsung’s Semiconductor Business dropped to KRW 16.09 trillion ($14.302 billion) in the second quarter, whereas operating profit totaled KRW 3.4 trillion ($2.877 billion). While Samsung’s memory businesses were weak, the company said that its foundry business demonstrated robust results.

According to Samsung, its contract production division saw strong demand for mobile SoCs made using 10LPP/8LPP technologies as well as mobile, HPC, automotive, and network products fabbed using 14LPx/10LPP processes. Overall, it is evident that Samsung Foundry makes loads of premium products using its leading-edge FinFET process technologies.

In the next several years Samsung Foundry will continue to use its 14 nm, 10 nm, and 7 nm nodes perfected for particular applications either by optimizations or by plugging in advanced modules.

Like other contract makers of semiconductors, Samsung refines each of its nodes in order to meet requirements of various applications and clients rather than leaps ahead with radically different nodes every 18 – 24 months (like makers of chips used to do traditionally). Considering all the difficulties that engineers have to overcome developing new manufacturing technologies, the approach allows Samsung to better manage its R&D costs and manufacturing risks.

7LPP Refinements: 6LPP, 5LPE, 4LPE

As expected, extreme ultraviolet lithography (EUVL) will be a key enabler for Samsung’s leading-edge next-generation fabrication processes. The first technology to use EUV is 7LPP and its successors will use it more extensively.

Later this year Samsung will initiate production of chips using its 6LPP process technology, which returned to its roadmap earlier. Samsung’s 6LPP is a refined version of Samsung’s 7LPP that offers higher (~10%) transistor density, lower power, but can re-use IP originally designed for 7LPP. In addition, 6LPP supports smart structures for clients willing to develop all-new new IP. As a result, Samsung Foundry’s clients will either be able to re-use their 7LPP IP without smart structures, or go with the latter, but will have to rely on new IP. In addition to smart structures, 6LPP will add support for things like multi diffusion break.

The next step in evolution of Samsung’s 7LPP production technology will be its 5LPE manufacturing process. This one provides more benefits when it comes to power, performance, and area than 6LPP, but can also reuse IP originally designed for the initial process. Samsung expects to tape out the first chips using its 5LPE technology in the second half of this year and expects to mass produce it in the first half of 2020.

Samsung Foundry expects 5LPE to become its main EUVL node in 2020 in terms of customer tape outs, probably because the technology will be able to offer numerous benefits for a wide variety of applications, whereas Samsung’s EUV yields will get higher. Another reason why 6LPP and 5LPE technologies will be used more widely than 7LPP process is because Samsung Foundry will have more EUV capacity in the coming months after it builds its EUV line in Hwaseong, which was architected for the EUV equipment from the start. The fab, which costs $4.615 billion, will be completed shortly and is projected to start high-volume manufacturing in 2020.

The pinnacle of Samsung’s 7LPP evolution will be the company’s 4LPE technology (and possibly 4LPP that is absent from the latest Samsung Foundry roadmap). The foundry will complete its development in the second half of this year, so expect the first tape out in 2020 and volume production sometimes in 2021.

Official Statement

The official statement by Samsung about its Foundry Business reads as follows:

“For the Foundry Business, results were robust on the back of strong demand from a major customer’s 8/10-nm mobile AP and image sensor products. In addition, new orders from customers increased in the 10/14-nm process and applications diversified to include mobile, HPC, automotive and network products. In the second half, earnings growth is expected to continue due to the ongoing expansion of orders for AP, image sensors and DDI as well as increased demand for HPCs, including crypto currency mining chips. The Company plans to start mass production of EUV 6-nm process and aims to strengthen its competitiveness through tape-out of the EUV 5-nm process and by completing 4-nm process development.”

Related Reading:

Source: Samsung

POST A COMMENT

34 Comments

View All Comments

  • Sychonut - Wednesday, July 31, 2019 - link

    But, BUT, and hear me out on this one, the real question is can it compete with Intel's 14nm+++++++? Reply
  • PeachNCream - Wednesday, July 31, 2019 - link

    Shhh! You're going to invoke HStewart. Reply
  • regsEx - Wednesday, July 31, 2019 - link

    Probably Intel should have do the same as Samsung and TSMC.
    Rename 14+ to 12 nm
    Rename 14++ to 10 nm

    Rename 10 to 7 nm
    Rename 10+ to 6 nm

    Rename 7 to 5 nm
    Reply
  • regsEx - Wednesday, July 31, 2019 - link

    No, wait. Intel 7 nm as dense as TSMC 3 nm, so 10++ would be 5 nm and 7 would be 3 nm. Reply
  • extide - Wednesday, July 31, 2019 - link

    Yeah, exactly all these guys are doing process revs, just calling it differently, but it's really the SAME THING! Reply
  • Teckk - Wednesday, July 31, 2019 - link

    Do we know Intel's EUV plan? Does it start with its 7nm? I'm guessing Samsung and TSMC have been pretty vocal in terms of EUV but Intel is surprisingly not. Won't it help Intel considering it manufactures more complex chips compared to other foundries? (IoT, memory, x86 client, server etc.) Reply
  • Teckk - Wednesday, July 31, 2019 - link

    Can't edit... But yeah, seems pretty aggressive from Samsung, both the claims and the marketing/naming. Reply
  • Kevin G - Wednesday, July 31, 2019 - link

    Samsung is being aggressive here now that EUV tools are available. Though their naming schema is heavy on the marketing. Still, they’ll be ahead of Intel for a bit.

    Thus far, I have yet to see what I would call a complex chip at 10 nm class or below in volume. The closest would be Vega 20 at 331 mm^2. The previous generation of nodes set a new record at 818 mm^2. Intel could start producing large dies before their competitors but everyone seems to be going in the direction of chiplets and advanced packaging technologies to work around yields.
    Reply
  • saratoga4 - Wednesday, July 31, 2019 - link

    >everyone seems to be going in the direction of chiplets and advanced packaging technologies to work around yields.

    With 2nd gen EUV, the reticle limit drops to ~400 mm^2, so vendors are getting ready for the end of large die parts.
    Reply
  • Yojimbo - Thursday, August 01, 2019 - link

    The reticle will still be 6", it's the on-wafer field size that drops due to using a half-field in order to keep the angles of the light down. If they switched to a larger mask (9 inches) they could maintain the same maximum die size but I don't think that's what they plan to do. I guess that would be very expensive? Anyway, all that is 4 years out at least. Semiconductor companies have been researching multi-die modules for over 5 years at least, before any determinations were made on what direction high NA EUV would go, and before it was even certain that any type of EUV would be the future. There are reasons to develop multi-die modules beyond a decrease in maximum die size using high NA EUV, such as flexibility in function through modularity (more economically targeting different markets with similar IP), flexibility in using different manufacturing processes for different parts of the chip (saving on cost for less critical functions, and I believe mixing analog and digital circuitry), more power efficient pooling of compute resources for parallel processors than allowed by inter-package communication such as CLX or NVLink, and allowing scalability of architectures from something targeting an edge device to something targeting a data center through the use of chiplets. Reply

Log in

Don't have an account? Sign up now