Samsung Foundry this week updated its fabrication technology roadmap, introducing a number of changes and announcing the first details about its 3 nm manufacturing process that is several years away. The company also reiterated plans to start risk production of chips using its 7LPP process technology and extreme ultraviolet lithography (EUVL) later this year.

Samsung is accelerating its foundry roadmap in a bid to not only keep up with rivals in the foundry industry, but also to enable its SoCs to take advantage of the leading-edge process technologies and offer higher performance or lower power consumption than competing chips. Higher performance and/or lower power allows Samsung to build better mobile devices, such as smartphones, which are the company’s bread and butter. Therefore, being a vertically-integrated company, it makes a great sense for Samsung to stay ahead of any other maker of semiconductors.

Samsung Foundry Lithography Roadmap, HVM Start
Data announced by company during conference calls, press briefings and in press releases
2017 2018 2019 2020 2021 2022 2022+
1H 2H 1H 2H 1H 2H 1H 2H
10LPE 10LPP 7LPP**
8LPP
10LPU*
7LPP 5LPE** 5LPE 4LPE* 4LPP* 3GAAE*
3GAAP*
*Exact timing not announced
**May be available only to Samsung LSI

7LPP on Track, 5LPP/6LPP Vanish, 5LPE Introduced

Samsung has previously announced plans to start risk production of chips using its 7LPP (7 nm low power plus) process technology and EUVL tools in 2018, and this target remains unchanged. What remains to be seen is when exactly Samsung starts high-volume manufacturing (HVM) of chips using this tech and ASML’s Twinscan NXE equipment. Since the company can offset the high initial costs of chips made on this process by selling complete smartphones (this is where Samsung’s vertical integration starts to pay off), it can kick off HVM of SoCs for the next generation Galaxy S smartphones using its latest fabrication process just months after it starts risk production using 7LPP. What is noteworthy is that Samsung admits that 7LPP IP blocks required for various chips will be ready only by the first half of 2019, so the tech is not ready for prime time just now (but could be ready for Samsung’s own SoCs), pending what smartphone Samsung intends to launch in 1H 2019.

Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to “allow greater area scaling and ultra-low power benefits” when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.

4LPE/4LPP to Retain FinFETs

Samsung's foundry update also laid out the company's plans for more advanced fabrication technologies that they plan to use in the coming years. As it appears, Samsung has decided to prolong the usage of FinFET transistors for leading-edge manufacturing processes. Last year Samsung planned to introduce gate-all-round FETs (GAAFETs) with its 4LPP node in 2020, but the plans have changed since then.

Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.

It is unclear when Samsung plans to start risk production and volume production using its 4LPE and 4LPP process technologies, but if everything goes in accordance with the company’s current process technology cadence, expect Samsung’s 4LPE/4LPP nodes to be used for HVM in the early 2020s.

3 nm to Use GAAFETs

The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung’s own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.

MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung’s fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the EUV in general will have a clear impact on Samsung’s technologies several years down the road.

Industry Lithography Roadmap, HVM Start
Data announced by companies during conference calls, press briefings and in press releases
  2017 2018 2019 2020 2021 2022 22+
1H 2H 1H 2H 1H 2H 1H 2H
GF 14LPP 12HP 12LP 7nm DUV 7nm EUV
1st Gen*
7nm EUV
2nd Gen*
? ?
Intel 14nm+ 14nm++ 10 nm* 10 nm+* ? ?
Samsung 10LPE 10LPP 7LPP**
8LPP
10LPU*
7LPP 5LPE** 5LPE 4LPE* 4LPP* 3GAAE*
3GAAP*
SMIC 14 nm in development ? ?
TSMC N10FF
N16FFC
N7FF
N12FFC
N12FFC
N12ULP
N7FF+ N5FF ? ?
UMC - 14nm no data  
*Exact timing not announced
**May be available only to Samsung LSI

Related Reading

Sources: Samsung, EETimes

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  • PeachNCream - Thursday, May 24, 2018 - link

    I refuse to be excited until companies start announcing negative numeric values for their manufacturing processes. For instance, I would like to see -5nm since that means using my phone will charge instead of discharge my battery and absorb rather than create heat, dumping it into some dark, ethereal realm that exists outside of the observable Universe. Then I can stick my phone in my crotch to cool it off in the summer and minimize unsightly sweat generation in my nether regions. That translates into milking another day or two out of my undergarments and saves me from doing as much laundry. Mom would be so proud of me! Reply
  • bug77 - Friday, May 25, 2018 - link

    Why stop there?
    Instead of negative, you should demand complex numbers. Those would be fun to have.
    Reply
  • TheWereCat - Sunday, May 27, 2018 - link

    So you will have to be carrying discharger with you everywhere to not overcharge and explode your batteries? Reply
  • PeachNCream - Tuesday, May 29, 2018 - link

    Nope! I'm okay with overcharging my phone's battery to the point that it bursts while in my pants. Reply
  • kf27fix - Thursday, May 24, 2018 - link

    3 more nm and we will be down to 0 nm. Then, things will start to look interesting... Reply
  • rahvin - Thursday, May 24, 2018 - link

    There are always smaller measurements. 0nm would be 100um. The problem is the Silicon atom is only 0.2nm wide so when you get to 1nm you are constructing wires that are only 5 atoms wide. Quantum effects at this size are likely to become so bad they simply can't go smaller.

    I remember an article from several years ago that talked about 5nm probably being the point where quantum effects may make shrinking things any more impossible. This should be obvious as even at 14nm and smaller they are having to dope the traces with all kinds of stuff (FinFET etc) to negate the quantum effects.
    Reply
  • nandnandnand - Friday, May 25, 2018 - link

    If you have a quantum effect problem below 3-5 nm, you switch to tunnel field effect transistors (TFETs) which actually use the effect to operate. Voila, problem solved.

    https://en.wikipedia.org/wiki/Tunnel_field-effect_...
    Reply
  • rahvin - Thursday, May 24, 2018 - link

    I thought Extreme UV (EUV) only worked till 7nm and after that they had to go to X-Ray lithography and none of the tools are even close to being ready.

    I thought that's why Intel had slowed down was because they didn't want to get stuck on 7nm for a decade waiting for the X-ray lithography tools to finally become available so they worked on stretching out the existing process tech while the tools people worked to make X-ray lithography viable.
    Reply
  • MrSpadge - Thursday, May 24, 2018 - link

    They expect to write 5 nm class processes with EUV and higher numerical apertures. It's not easy, as always with EUV, but probably not a show stopper. Afterwards they'll probably need multi patterning with EUV (as with the current 193 nm tools). Reply
  • FullmetalTitan - Friday, May 25, 2018 - link

    High NA is definitely the path forward with EUV, same as it was with KrF lasers. There are some obvious challenges in scaling EUV re: optics, but it should also be noted that critical dimensions like gate half-pitch at "5nm" are still on the order of ~15-20nm. The longterm future of semicon will involve a LOT of new materials science and novel transistor designs, but silicon probably has legs through what most companies will call 2/3nm nodes. Reply

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