TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC’s 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC’s Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

TSMC's Fab 18: Milestones
  Phase 1 Phase 2 Phase 3
Construction Start Early 2018 Q3 2018 Q3 2019
Equipment Move-In Early 2019 ? ?
High-Volume Manufacturing Start Early 2020 2020 2021

The Fab 18 will have a total floor area of 950,000 square meters and its cleanroom area will exceed 160,000 square meters, the contract maker of semiconductors said. TSMC estimates that the combined production capacity of all three phases of the Fab 18 will exceed one million 300-mm wafer starts per year, which is comparable to the capacities of the other GigaFabs that TSMC operates — Fab 12, Fab 14, and Fab 15. It is noteworthy that the planned floor area and cleanroom space of the Fab 18 will be significantly larger than the initially planned floor and cleanroom area of the Fab 15, which emphasizes increasing complexity of IC manufacturing these days as well as increasing orders from TSMC's clients.  In total, the Fab 18 will cost TSMC NT$500 billion ($17.08 billion), making it one of the most expensive chip manufacturing facilities in the world.

Brief Comparison of TSMC's Fab 15 and Fab 18
  Fab 15 Fab 18
Total Area of Site 18.4 hectares ?
Building Area 430,000 m² 950,000 m²
Clean Room Space* 104,000 m² 160,000 m²
Initially Expected Investment** NT$300 billion
~$9.375 billion
NT$500 billion
~$17.08 billion
Groundbreaking July 2010 January 2018
Notes *Fabs are usually upgraded over time, today's cleanroom space of the Fab 15 may be larger than initially projected.
**Initially expected investments tend to change over time.

Besides its dimensions and cost, there is another reason why Fab 18 is important for the semiconductor industry: it will be one of the world’s first facilities to produce chips using a 5-nm production tech. TSMC yet has to detail its 5 nm manufacturing technology, but from the announcements that the company has made so far it is evident that this fabrication process will rely significantly on EUV lithography. TSMC did not mention EUV at all in its press release, which is a bit strange. Meanwhile, over the course of last year the semiconductor manufacturer did mention that the 5 nm fabrication technology would be its second-gen EUV process, which means usage of EUV for more more layers when compared to the CLN7FF+ (its advanced 7 nm tech). Furthermore, TSMC already has functional SRAM cells made using its CLN5FF technology and the yields were satisfactory in mid-2017. Therefore, the 5 nm development process seems to be going on relatively well.

The extended usage of EUV for 5-nm chip production means that the company will need to install more EUV tools into the Fab 18, which is one of the reasons why it needed to expand the fab’s cleanroom space. The fact that TSMC has begun to build Fab 18 indicates that the contract maker of chips is confident in its 5 nm technology as well as EUV equipment, including ASML’s TWINSCAN NXE scanners, Cymer’s EUV light sources and other tools. This confidence is further underscored by their intention to start high-volume manufacturing of 5-nm devices in Fab 18 in early 2020.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  7FF
vs
16FF+
7FF
vs
10FF
7FF EUV
vs
7FF
5FF EUV
vs
7FF EUV
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10% tangible
HVM Start ~Q2 2018 - ~H2 2019 H1 2020

Related Reading:

Sources: TSMC (1, 2, 3, 4)

POST A COMMENT

24 Comments

View All Comments

  • soliloquist - Wednesday, January 31, 2018 - link

    Given all the trouble that Intel has had with bringing 10nm to market, I will believe those time tables when I see it. Reply
  • FunBunny2 - Wednesday, January 31, 2018 - link

    you can't fool Mother Nature, or Heisenberg. Reply
  • gfkBill - Wednesday, January 31, 2018 - link

    Intel 10nm != TSMC 5nm Reply
  • gfkBill - Wednesday, January 31, 2018 - link

    D'oh - Intel 10nm IS probably equivalent to TSMC 5nm, was my typo-ridden point. Everyone other than Intel uses a difference metric, to make themselves sound better than they are basically.

    (Dammit, why we can't Edit comments, Anandtech?)
    Reply
  • Wilco1 - Wednesday, January 31, 2018 - link

    No Intel's 10nm doesn't even use EUV so it's in not nearly as advanced as TSMC 5nm, and can't even beat the density of TSMC 7nm. The world has changed, Intel lost its leadership in chip technology last year. Reply
  • Santoval - Thursday, February 01, 2018 - link

    Intel was way too ambitious with their 10nm node, jumping from 37.5 million transistors per mm^2 at 14nm to ~101 million transistors per mm^2 at 10nm, a 2.7x higher transistor density. It appears that this ambition is one of the reasons of the delay of the 10nm launch, perhaps the primary reason.

    TSMC and Samsung at 10nm are at 45 - 53 million transistors per mm^2 (let's assume an average of 50 million), which is barely denser than Intel's 14nm. Do you seriously think that either they or GloFo, EUV or not, will manage to go beyond 100 million transistors at 7nm? Intel was more ambitious with their 10nm node due to the very long delay (they needed to "catch up"), but that reason does not apply to the others.

    EUV is not a magic bullet. It merely helps companies reduce the number of steps but its issues have not all yet been resolved. At first it will only be used for some critical layers, with the rest being done by plain old 193nm ArF lithography. There is a reason Intel wants to focus on comparing transistor densities of the FEOL stack while the others insist on quoting meaningless xxnm marketing numbers.
    Now, if Intel does not release 10nm CPUs in 2018 either (or even if they release the first in Q4 2018) it will surely fall back. But as of yet it hasn't.
    Reply
  • name99 - Thursday, February 01, 2018 - link

    Right, Intel was “too ambitious”.
    This sort of BS excuse may work in American politics, but the rest of the world is not quite as stupid as the average American voter.

    This is how the American century ends, as the Americans retreat into an ever more detached fantasyland, spreading from culture to politics, now to business.
    Reply
  • HStewart - Wednesday, January 31, 2018 - link

    This whole nm size stuff reminds me of days of Frequency wars back in Pentium 4 days - but sort of in reverse. We are actually not sure exactly what Intel's 10nm is like - but it like be more dense that other processes significantly. This is why it taking longer get out. I believes Intel's process is 3D process.

    In any case, what matters is how many transistors / components can be in square area and not nm metric.

    Most exiting thing about Intel's processes is that it can combine multiple processes on the same die. This means important components like CPU / GPU / Memory can be on denser material why the IO and less important components can be done on less denser. I don't believe Intel is using this for combo Intel CPU / AMD GPU component - that things reminds me of last Celeron / Pentium components - which have more in common with Atom that higher level processors. I was frustrated with my Lenovo 100s 14in - I could not update memory.

    I hope none of my comments have mistakes - because I wish we could edit comments here.
    Reply
  • Wilco1 - Thursday, February 01, 2018 - link

    "In any case, what matters is how many transistors / components can be in square area and not nm metric."

    7nm TSMC density is 116 million transistors/mm^2, while Intel 7nm does ~100. See https://www.semiwiki.com/forum/content/6713-14nm-1...

    "I hope none of my comments have mistakes"

    Well pretty much all of our post is FUD or fake news as it is called nowadays. Combining multiple processes on the same die? 3D process? What pills did you take?
    Reply
  • Santoval - Thursday, February 01, 2018 - link

    I checked out the article you linked and apparently I was wrong above. It says Samsung's 7nm is going to have 127.3 MTr/mm^2 and TSMC's 7nm will have 116.7 MTr/mm^2. I had no idea they were so ambitious. Since Intel will retain 10nm for at least three CPU generations I will concede that they have fallen behind Samsung and TSMC (and GloFo?) even if the others' 7nm node is released two, three or even four quarters after Intel's 10nm. Reply

Log in

Don't have an account? Sign up now