Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here. In fact, keeping in mind that both TSMC and Samsung are already talking about their second-gen EUV technologies (which they call 5 and 6 nm) that will use more EUV layers, it looks like the foundries are confident of the ASML TwinScan NXE manufacturing tools (as well as of the Cymer light source, pellicles, photoresists, etc.) they are going to use.

10 nm: Samsung Is Shipping, TSMC Is Steady Beyond 10 nm at Samsung: 8 nm and 6 nm


View All Comments

  • Demon-Xanth - Friday, May 05, 2017 - link

    A silicon atom's width is about 110pm, so they are literally going into widths that are only double digit numbers of atoms wide. Reply
  • MananDedhia - Friday, May 05, 2017 - link

    Processes that deposit single atomic layers are already used commonly in processes - even in 28nm.....For some layers, atomic layer deposition is the only way to go. The complexity increased here because we are now increasing the number of layers and devices that need to be defined at those scales. Reply
  • bug77 - Friday, May 05, 2017 - link

    Yes, but you can't take 3 atoms, call then source, drain and gate and assemble them into a transistor. Reply
  • ddriver - Friday, May 05, 2017 - link

    Why not? IBM have already demoed atomic assembly. The downside - it is very slow, it is one atom at a time VS etching septillions of atoms with acid at the same time.

    BTW I finally get how they will get to 5 nm - by lying about it. How much of a 10nm chip's features are at 10nm resolution? Not many. Area decrease is already falling behind the process scale number and it is only going to get worse.

    On the upside - no biggie - we already have enough performance to run terminators. So our extinction is well assured.
  • philehidiot - Friday, May 05, 2017 - link

    Don't you go worrying about terminators. I've already started work on the first of many. I was just so sick of not being able to get a seat on the bus. Was thinking no one wants to sit next to a cybernetic killing machine so I can send that to the earliest bus stop, get it to reserve a seat and I can ride to work without the smell of unwashed, practically rotting human being next to me.

    Far safer than one of those self driving car things. Bloody death traps.
  • Kevin G - Sunday, May 07, 2017 - link

    Are you Sarah Conner? Reply
  • Xajel - Sunday, May 07, 2017 - link

    Yeah they're actually moving these actual atoms... atom by atom like a lego Reply
  • Kevin G - Sunday, May 07, 2017 - link

    The node size is mostly marketing now which is why Intel went out of their way to define some new metrics ~6 weeks ago. While I wasn't a fan of that marketing spiel, there is a point that there needs to be a new metric as traditional node shrinks are few and far between going forward.

    What I think the foundries are waiting on is a new big break through as they realize that they cannot currently continue on the existing path indefinitely. Germanium can come in as an exotic material as a substitute for silicon but wafer prices are extremely expensive. Even then, germanium doesn't even solve the node problem but rather just provides better material properties at existing nodes. Carbon nanotubes and graphene are two related materials seen as potential for replacing silicon as we get even closer to the atomic level. Both have some good properties for circuit design but no one has found a means of economical mass production.

    Both Intel and IBM has invested heavily into silicon photonics. So far their efforts have lead to advancements in IO but not raw processing but optical logic gates do exist. Much like other exotic solutions, these suffer from mass production problems to bring them out of the research lab. (Notice a trend starting here?)

    I think strategies like interposers and EMIB are emerging to side step the absolute need for shrinks in the sense of limiting transistor counts. Granted interposers/EMIB do nothing with regards to power consumption. The one nice thing about these techniques is that they do potentially allow for mixing some of the more exotic solutions with bulk processes. For example, a die with slicon photonics could interface with some high speed optical circuits in the package and also interfaces with more traditional bulk processes for its SRAM cache. Very expensive but worth considering when there are other new node alternatives available. Granted, such choices are not going to happen tomorrow but they're clearly on the horizon.
  • eachus - Sunday, October 01, 2017 - link

    My read is that the first application of nanotubes or graphene will be laying down a copper layer, then growing graphene on top of it. The trick will be to get the graphene to align on top of the copper, which will probably take another layer in between, perhaps silver. Could silver be substituted for copper in bulk? Good question. It is a better conductor and solves the alignment problem.

    You may think of silver as a precious metal along with gold and platinum, but over fifty per cent of the silver mined goes into silver solder for brazing or soldering metals together. Most silver solder is used for brazing, go figure. Silver is also used in thermal compounds for getting a good seal between a CPU chip and the heat sink. Obviously replacing a few grams of copper with silver inside the chip won't raise prices significantly.

    Getting copper to bond to the graphene is not a problem--even if the reverse is a significant problem. However high-temperature processes may damage the graphene. Best is probably a "wet" process to put a thin layer of copper on the graphene before building the next litho layer. Putting the graphene in a copper sandwich like this should significantly improve the characteristics of the layer. This will show up as a reduced capacitance with adjacent conducting traces--less cross-talk and faster signal propagation.
  • beginner99 - Monday, May 08, 2017 - link

    "BTW I finally get how they will get to 5 nm - by lying about it"
    Process tech numbering hasn't been about feature size for the past 2 decades.

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