Floating Point

The key highlight improvement for floating point performance is full AVX2 support. AMD has increased the execution unit width from 128-bit to 256-bit, allowing for single-cycle AVX2 calculations, rather than cracking the calculation into two instructions and two cycles. This is enhanced by giving 256-bit loads and stores, so the FMA units can be continuously fed. AMD states that due to its energy aware scheduling, there is no predefined frequency drop when using AVX2 instructions (however frequency may be reduced dependent on temperature and voltage requirements, but that’s automatic regardless of instructions used)

In the floating point unit, the queues accept up to four micro-ops per cycle from the dispatch unit which feed into a 160-entry physical register file. This moves into four execution units, which can be fed with 256b data in the load and store mechanism.

Other tweaks have been made to the FMA units than beyond doubling the size – AMD states that they have increased raw performance in memory allocations, for repetitive physics calculations, and certain audio processing techniques.

Another key update is decreasing the FP multiplication latency from 4 cycles to 3 cycles. That is quite a significant improvement. AMD has stated that it is keeping a lot of the detail under wraps, as it wants to present it at Hot Chips is August. We’ll be running a full instruction analysis for our reviews on July 7th.

Decode Integer Units, Load and Store
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  • Smell This - Sunday, June 16, 2019 - link


    AND ...
    it might be 12- to 16 IF links or, another substrate ?
    Reply
  • Targon - Thursday, June 13, 2019 - link

    Epyc and Ryzen CCX units are TSMC, the true CPU cores. The I/O unit is the only part that comes from Global Foundries, and is probably at TSMC just to satisfy the contracts currently in place. Reply
  • YukaKun - Monday, June 10, 2019 - link

    "Users focused on performance will love the new 16-core Ryzen 9 3950X, while the processor seems nice an efficient at 65W, so it will be interesting so see what happens at lower power."

    Shouldn't that be 105W?

    And great read as usual.

    Cheers!
    Reply
  • jjj - Monday, June 10, 2019 - link

    The big problem with this platform is that ST perf per dollar gains are from zero to minimal, depending on SKU.
    They give us around 20% ST gains (IPC+clocks) but at a cost. Would rather have 10-15% gains for free than to pay for 20%. Pretty much all SKUs need a price drop to become exciting, some about 50$, some a bit less and the 16 cores a lot more.

    Got to wonder about memory BW with the 16 cores. 2 channels with 8 cores is one thing but at 16 cores, it might become a limiting factor here and there.
    Reply
  • Threska - Tuesday, June 11, 2019 - link

    That could be said of any processor. "Yeah, drop the price of whatever it is and we'll love you for it." Improvements cost, just like DVD's costed more than VHS. Reply
  • jjj - Tuesday, June 11, 2019 - link

    In the semi business the entire point is to offer significantly more perf per dollar every year. That's what Moore's Law was, 2x the perf at same price every 2 years. Now progress is slower but consumers aren't getting anything anymore.

    And in pretty much all tech driven areas, products become better every year, even cars. When there is no innovation, it means that the market is dysfunctional. AMD certainly does not innovate here, except on the balance sheet. Innovation means that you get better value and that is missing here. TSMC gives them more perf per dollar, they have additional gains from packaging but those gains do not trickle down to us. At the end of the day even Intel tries to offer 10-15% perf per dollar gains every cycle.
    Reply
  • AlyxSharkBite - Tuesday, June 11, 2019 - link

    That’s not Moore’s Law at all. It stated that the number of transistors would double. Also it’s been dead a while

    Sandy bridge 4c 1.16b
    Coffee lake 4c is 2.1b (can’t compare the 6c or 8c)

    And that’s a lot more than 2 years.
    Reply
  • mode_13h - Tuesday, June 11, 2019 - link

    Yeah, but those two chips occupy different market segments. So, you should compare Sandybridge i7 vs. Coffelake i7. Reply
  • Teutorix - Tuesday, June 11, 2019 - link

    The number of transistors in an IC, not the number of transistors per CPU core. This is an important distinction since a CPU core in Moore's day had very little in it besides registers and an ALU. They didn't integrate FPUs until relatively recently.

    It's about overall transistor density, nothing more. You absolutely can compare an 8c to a 4c chip, because they are both a single IC.

    An 8 core coffee lake chip is 20% smaller than a quad core sandy bridge chip. That's double the CPU cores, double the GPU cores, with probably a massive increase in the transistors/core also.

    Moore's law had a minor slowdown with intel stuck at 14nm but its not dead.
    Reply
  • Wilco1 - Tuesday, June 11, 2019 - link

    Moore's Law is actually accelerating. Just not at Intel. See https://en.wikipedia.org/wiki/Transistor_count - the largest chips now have ~20 Billion transistors, and with 7nm and 5nm it looks like we're getting some more doublings soon. Reply

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