One of the interesting elements that came out of some of our discussions at the IEDM conference this year revolves around the present deployment of EUV. Currently only one company makes EUV tools, ASML, and the deployment of these to the various foundries that are on the leading edge has been a topic of some discussion here at the event, especially as we start talking about 7nm, 5nm, 3nm, and new generations of tools.

One of the interesting metrics that we’ve seen from ASML is the total number of 300mm wafers that have been enabled through EUV. Early adoption of EUV actually started all the way back in 2013, and it took until 2017 to push through over 1,000,000 wafers. In 2018 another 900,000 wafers were processed, and through 2019, with chips such as Huawei’s Kirin 990 5G, Qualcomm’s upcoming Snapdragon 700 series, and Samsung’s own EUV efforts, another 2.5 million wafers have been processed, showing an explosive CAGR of 95% since 2016.

Along with that, ASML’s NXE:3400B Step and Scan machines have been at the heart of most of this EUV production. As the graph above shows, 38 machines were installed by Q2 2019, and through 2019 the B versions have been replaced with the NXE:3400C editions, which can process at peak 175 wafers per hour.

One of the advantages of the NXE:3400C models is the modularity in its design, meaning that a mirror defect should take only an 8-10 hour replacement, rather than take the machine out of action for a full 48 hours.

A note on EUV machine uptime is a key metric: ASML states that their average uptime (a 13-week moving average) is around 75%. This includes a series of ongoing updates to the machines, whcih take about 10% of that downtime: customers who want persistance on their machines without direct updates (or less frequent updates) end up with an average uptime of around 85%.

(Update: originally this article quoted uptimes from a different machine due to a miscommunication. The article has been updated to reflect ASML's latest numbers.)

 

ASML is keen to promote its improvement in wafer throughput of its NXE machines, from a little over 10 wafers per hour in 2014 to 170-175 in 2019.

Beyond the NXE lines of machines will be the EXE:5000 series. What makes these machines different is that they are built for the equivalent of TSMC’s 3nm / Intel’s 5nm processes by using ‘High-NA’ technology, technically moving from 0.33 NA optics to 0.55 NA optics, which will help improve manufacturing features at smaller and smaller resolutions. It will be interesting to see if the speed of the High-NA EXE machines will be similar or better to the NXE machines. Based on ASML’s presentation, High-NA machines should be coming into the market by 2023, by which time EUV use should be extensive at the leading edge.

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  • FreckledTrout - Wednesday, December 11, 2019 - link

    Everytime I see High-NA I think of hypernatremia but then I have to remind myself NA is not standing for sodium its numerical aperture. Reply
  • Death666Angel - Wednesday, December 11, 2019 - link

    And that's why capitalization is important. :D Reply
  • Freeb!rd - Thursday, December 12, 2019 - link

    I thought it meant Highly-NotAvailable... like the Infinite Improbability Drive. ; )
    https://www.youtube.com/watch?v=UIUIO1ImtJo
    Reply
  • katsetus - Thursday, December 12, 2019 - link

    Oh, that makes sense. I was just thinking when are they going to put turbos on their Naturally Aspirated EUV machines.
    It is good practice to spell out what abbreviations mean when first using them in an article, even if they should be unambiguous to the reader.
    Reply
  • Diogene7 - Wednesday, December 11, 2019 - link

    Really looking forward seeing devices with TSMC 5nm chip inside : it is kind of a key milestone for humanity to finally have consumer devices (smartphones) available with chips based on 5nm EUV lithography, having 10 of billions of transistors in less than 100mm2 !!! Reply
  • Santoval - Wednesday, December 11, 2019 - link

    That's the density of TSMC's 7nm+ node (they mentioned a transistor density ~115 MTr/mm^2, which translates to 11.5 billion transistors per 100 mm^2). TSMC's 5nm node will have a density of at least 180 MTr/mm^2. That is ~18 billion transistors per 100 mm^2, or ~13 billion transistors per 73 mm^2 (the die size of Snapdragon 855). Reply
  • Fataliity - Wednesday, December 11, 2019 - link

    Hey Ian, judging by the Intel slide's (2018 week # - 2019 week #), don't you think Intel is actually using EUV for 10nm and that's why it took so long to be up and running? Also explains low volume -- If they can't get more machines, then how are they going to increase capacity? Their chart seems to match the failed i3 10nm graphic disabled chip up to current generation.

    Think about it...
    Reply
  • Fataliity - Wednesday, December 11, 2019 - link

    Also it would be nice to compare this chart to their quarterly earnings where they reference progress on 10nm... I don't have time right now, but im very curious how it would match up with their message to shareholderss. Reply
  • extide - Wednesday, December 11, 2019 - link

    No. It's only in dev. Reply
  • Santoval - Wednesday, December 11, 2019 - link

    No they don't. They have zero reasons to use EUV for 10nm "in secret". That makes no business or any other kind of sense, since keeping this hypothesized clandestine EUV use under wraps would only hurt their stock price.
    On the contrary, if they were already using EUV they would have announced it long ago. They would have been obligated to their shareholders to announce it, to be more precise. This would go far beyond a lie by omission, since they have repeatedly reported that their 10nm node is based on DUV + SAQP (Self Aligned Quad Patterning).
    Reply

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