Today we’re covering some news of the more unusual type, and that is a roadmap update from Ampere, and having a closer look what the company is planning in terms of architectural and microarchitectural choices of their upcoming next-generation server CPUs in 2022 and onwards.

For people not familiar with Ampere, the company was founded back in 2017 by former Intel president Renée James, notably built upon a group of former Intel engineers who had left along with her to the new adventure. Initially, the company had relied on IP and design talent from former AppliedMicro’s X-Gene CPUs and still supporting legacy products such as the eMAG line-up.

With Arm having starting a more emphasised focus on designing and releasing datacentre and enterprise CPU IP line-ups in the form of the new Neoverse core offerings a few years back, over the last year or so we had finally seen the fruits of these efforts in the form of the release of several implementations of the first generation Neoverse N1 server CPU cores products, such as Amazon’s Graviton2, and more importantly, Ampere’s “Altra Quicksilver” 80-core server CPU.

The Altra Q line-up, for which we reviewed the flagship Q80-33 SKU last winter, was inarguably one of the most impressive Arm server CPU executions in past years, with the chip being able to keep up or beat the best AMD and Intel had to offer, even extending that positioning against the latest generation Xeon and EPYC generation.

Ampere’s next generation "Mystique" Altra Max is the next product on the roadmap, and is targeted to be sampling in the next few months and released later this year. The design relies on the same first generation Arm Neoverse N1 cores, at the same maximum 250W TDP as a drop-in replacement on the same platform, however with an optimised implementation that now allows for up to 128 CPU cores – 60% more cores than the first iteration of Altra we have today, and double the amount of cores of competitor systems from AMD or Amazon’s Graviton2.

For the future for designs beyond the Altra Max, Ampere is promising that they will be continuing emphasis of what they consider “predictable performance” for workloads with scaling socket load, increasing core counts with a linear increase in performance, and what I found interesting as a metric, to continue to reduce power per core – something to keep in mind as we’re discussing the next big news today:

Replacing Neoverse with Full Custom Cores

Today’s big reveal comes in regard to the microarchitecture choices that Ampere is going to be using starting in their next generation 2022 “Siryn” design, successor to the Altra Max, and relates to the CPU IP being used:

Starting with Siryn, Ampere will be switching over from Arm’s Neoverse cores to their new in-house full custom CPU microarchitecture. This announcement admittedly caught us completely off-guard, as we had largely expected Ampere to continue to be using Arm’s Neoverse cores for the foreseeable future. The switch to a new full custom microarchitecture puts Ampere on a completely different trajectory than we had initially expected from the company.

In fact, Ampere explains that what the move towards a full custom microarchitecture core design was actually always the plan for the company since its inception, and their custom CPU design had been in the works for the past 3+ years.

In terms of background - the design team leading the effort is lead by Ampere’s CTO Atiq Bajwa, who is also acting as the chief architect on the project. Bajwa and the team surrounding him appear to be mostly comprised of high-profile ex-Intel engineers and veterans which had left the company along with Renée James in 2017, topped-off with talent from a slew of other companies in the industry who joined them in the effort. The pedigree and history of the team is marked by achievements such as working on Intel’s Haswell and Broadwell processors.

Ampere’s explanation and rationale for designing a full custom core from the ground up, is that they are claiming they are able to achieve better performance and better power efficiency in datacentre workloads compared to what Arm’s Neoverse “more general purpose” designs are able to achieve. This is quite an interesting claim to make, and contrasts Arm’s projections and goals for their Neoverse cores. The recent Neoverse V1 and N2 cores were unveiled in more detail last month and are claimed to achieve significant generational IPC gains.

For Ampere to relinquish the reliance on Arm’s next-gen cores, and instead to rely on their own design and actually go forward with that switch in the next-gen product, shows a sign of great confidence in their custom microarchitecture design – and at the same time one could interpret it as a sign of no confidence in Arm’s Neoverse IP and roadmap. This comes at a great juxtaposition to what others are doing in the industry: Marvell has stopped development of their own ThunderX CPU IP in favour of adopting Arm Neoverse cores. On the other hand, not specifically related to the cloud and server market, Qualcomm earlier this year have acquired Nuvia, and their rationale and explanation was similar to Ampere’s in that they’re claiming that the new in-house design capabilities offered performance that otherwise wouldn’t have been possible with Arm’s Cortex CPU IP.

In our talks with Jeff Wittich, Ampere’s Chief Product Officer, he explains that today’s announcement should hopefully help paint a better picture of where Ampere is heading as a company – whether they’d continue to be content on “just” being an Arm IP integrator, or if they had plans for more. Jeff was pretty clear that in a few years’ time they’re envisioning and aiming for Ampere to be a top CPU provider for the cloud market and major player in the industry.

In terms of technical details as to how Ampere’s CPU microarchitecture will be different in terms of approach and how and why they see it as a superior performer in the cloud, are questions to which we’ll have to be a bit more patient for hearing answers to. The company wouldn’t comment on the exact status of the Siryn design right now – on whether it’s been taped in or taped out yet, but they do retierate that they’re planning customer sampling in early 2022 in accordance to prior roadmap disclosures. By the tone of the discussions, it seems the design is mostly complete, and Ampere is doing the finishing touches on the whole SoC. Jeff mentioned that in due time, they also will be doing microarchitectural disclosures on the new core, explaining their design choices in things like front-end or back-end design, and why they see it as a better fit for the cloud market.

Altra Max later this year, more cloud customer disclosures

Beyond the longer-term >2022 plans, today’s roadmap updates also contained a few more performance claim reiterations of Ampere’s upcoming 128-core Altra Max product, which is planned to hit the market later in the second half of the year and customers being sampled in the next few months.

The “Mystique” code-named Altra Max design will be characterised in that it’s able to increase the core-count by 60% versus the current generation Altra design, all while remaining at and below the same 250W TDP. The performance slides here are showcasing comparisons and performance claims against what is by now the previous generation competitor products, Ampere here simply explains they haven’t been able to get their hands on more recent Milan or Ice Lake-SP hardware to test. Nevertheless, the relative positioning against the Altra Q80-30 and the EPYC 7742 would indicate that the new chip would easily surpass the performance of even AMD’s latest EPYC 7763.

In the slide, Ampere actually discloses the SKU model name being used for the comparison, which is the "Altra Max M128-30" – meaning for the first time we have confirmation that all 128 cores are running at up to 3GHz clock speed, which is impressive given that we’re supposed to be seeing the same TDP and power characteristics between it and the Q80-33. We’ll be verifying these figures in the next few months once we get to review the Altra Max.

Today’s announcement also comes with an update on Ampere’s customers. Oracle was notably one of the first Altra adopters, but today’s disclosure also includes a wider range of cloud providers, with big names such as ByteDance and Tencent Cloud, two of the biggest hyperscalers in China.

Microsoft in particular is a big addition to the customer list, and while Ampere’s Jeff Wittich couldn’t comment on whether Microsoft has other internal plans in the works, he said that today’s announcement should give more clarity around the rumours of the Redmond company working on Arm-based servers, reports of which had surfaced back in December. Microsoft’s Azure cloud service is only second to Amazon’s AWS in terms of size and scale, and the company onboarding Altra products is a massive win for Ampere.

Taking control of one’s own future

Today’s announcements by Ampere of them deploying their own microarchitecture in future products is a major change in the company’s prospects. The news admittedly took us by surprise, but in the grand scheme of things it makes a lot of sense given that the company aims to be a major industry player in the next few years – taking full control of one’s own product future is critical in terms of assuring that success.

While over the years we’ve seen many CPU design teams be disbanded, actually having a new player and microarchitecture pop up is a much welcome change to the industry. While the news is a blow to Arm’s Neoverse IP, the fact that Ampere continues to use the Arm architecture is a further encouragement and win for the Arm ecosystem.

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  • sgeocla - Thursday, May 20, 2021 - link

    Aren't you going to mention any of the workloads where even the 28 core 8280 beats the 80 core Altra? And now there's the 40 core Ice Lake version and Sapphire Rapids incoming.
    AMD hasn't been able to ramp up even with 2x performance gap over Xeons because it's not just about superior performance. The platform needs to be stable (they just destabilized it by going custom with in-house cores) and engineering support must be there. Customers aren't going to wait months for their tickets to be solved just because Ampere doesn't have the thousands of engineers necessary to support their ramp.
    Reply
  • Wilco1 - Thursday, May 20, 2021 - link

    There was only one workload where Altra did really badly (SPECjjb), but in almost all other workloads (SPECINT_rate, LLVM compile, NAMD) even 2x 8280 was not able to match a single Altra. In SPECFP_rate 2x 8280 was barely faster than 1x Altra. The incoming Icelakes have to compete with Altra Max. Reply
  • mode_13h - Friday, May 21, 2021 - link

    > in almost all other workloads (SPECINT_rate, LLVM compile, NAMD)
    > even 2x 8280 was not able to match a single Altra.

    You're perhaps focusing too much on highly-scalable workloads. Both brands of x86 CPUs are still well ahead in per-core (if not per-thread) performance.
    Reply
  • Wilco1 - Friday, May 21, 2021 - link

    Altra beats the 7742 on per-core performance and is only 6% behind 7763: https://images.anandtech.com/graphs/graph16529/119...

    As for per-thread, Altra has 62% higher performance than 7763! So per-thread performance is absolutely awful on x86, I don't see how you can possibly claim x86 is ahead with a straight face.
    Reply
  • mode_13h - Friday, May 21, 2021 - link

    > As for per-thread, Altra has 62% higher performance than 7763!
    > So per-thread performance is absolutely awful on x86

    Yeah, but you surely know that's an apples vs. oranges comparison. The marginal cost of the hyperthreads is like 10% more area. So, it ends up being a win to add SMT. Otherwise, they wouldn't do it.

    And let's not forget that, when you're comparing per-thread performance, the 7763 has 128 threads vs. only 80 threads in the Q80-33. So, the concept of having 2x as many threads that are less performant is cut from the same conceptual cloth as Ampere's idea of using a larger number of slower ARM cores. You can't really criticize the SMT of x86 CPUs without implicitly criticizing ARM and Ampere's approach of making up for the slowness of their cores by using more of them.

    And AMD nets 12% better aggregate performance and a win on SPECint2017 Base Rate-N from the technique. If the shoe were on the other foot, you'd be trumpeting how smart a move it is for ARM to be doing it.

    But we can all now see you're not here to have a good faith discussion of the relative strengths and weaknesses of these CPUs. You're cherry-picking and spinning literally every single thing you can, to make Altra look like it dominates, when it's merely competitive.
    Reply
  • Wilco1 - Saturday, May 22, 2021 - link

    Assuming SMT adds 10% area on x86, getting just 12% better throughput is not a great advertisement for SMT. There are of course scenarios where SMT does better, but I don't believe SMT makes much sense in servers. With Arm's smaller cores, it's better to add more cores.

    When Altra Max benchmarks are out, you will see that adding real cores works out better than adding SMT. Altra Max will outperform Milan by a good margin at lower power. Its performance per thread will also be higher than an SMT thread on Milan.

    If you still didn't get the importance of the historical achievement of a licensed Arm server core beating Intel/AMD's latest and greatest, Altra Max will surely do it.
    Reply
  • deltaFx2 - Saturday, May 22, 2021 - link

    Intel states smt area and power cost is less than 5%. So it’s almost for free for 2way smt. https://software.intel.com/content/www/us/en/devel...
    Moreover smt can be turned off if your application does not need it such as some cases of HPC.

    And dream on… if adding cores by cutting caches results in higher per thread performance then caches have no merit. Which is utter nonsense. Altra 128c is rumored to have 16MB total LLC to make room for more cores. altra 128c is spec rate accelerator not a general purpose server. See spec jbb results. Altra is calxeda redux: posts high spec rate scores, with crap latency performance under load.
    Reply
  • mode_13h - Sunday, May 23, 2021 - link

    > Intel states smt area and power cost is less than 5%.

    Thanks. I don't know where I got the 10% figure. Maybe I imagined it, or maybe it dates back to simpler core designs.
    Reply
  • Wilco1 - Sunday, May 23, 2021 - link

    Those kinds of claims are likely as trustworthy as 10nm status claims - without a detailed paper explaining which buffers were duplicated, how many bits were added to all the cache structures to differentiate between threads, it's hard to know how it was computed.

    Some Arm core have SMT so the cost on Arm design is known (but not public). Those cores haven't been big successes, and no new SMT cores have been announced since, so that suggests it is not as easy or cheap as claimed. Given the myriad of security issues with SMT, I'm not expecting future designs to have SMT either.

    Read what I said: Altra Max will beat Milan on overall performance and per-thread performance. Adding more cores will of course reduce performance per core due to cache/bandwidth limitations, but throughput still goes up significantly. Altra Max is special purpose like A64FX - with Arm you will see different designs targeting specific niches.
    Reply
  • mode_13h - Monday, May 24, 2021 - link

    > that suggests it is not as easy or cheap as claimed.

    Or, maybe just that it doesn't make as much sense on mobile, which is still ARM's top priority. So far, all their server cores are still derived from mobile ones.

    > Given the myriad of security issues with SMT

    This is another potential explanation why ARM didn't bother to pursue SMT. However, recent kernel work by Google & others have eliminated SMT-related security issues by optionally preventing threads from different processes from sharing a physical core.

    > Altra Max will beat Milan on overall performance and per-thread performance.

    If they indeed accomplish that by further reducing LLC, then it could be somewhat of a Pyrrhic victory. It will be telling if a number of benchmark scores actually *drop*, relative to the 80-core model.
    Reply

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