Just like all major makers of DRAM, SK Hynix produced its first DDR5 memory chips a couple of years ago and has been experimenting with the technology since then. To that end, it is not surprising that the company displayed its DDR5 RDIMM at CES 2020, which implies that development is proceeding as planned.

At the trade show, SK Hynix demonstrated its 64 GB DDR5 RDIMM with ECC rated for a 4800 MT/sec/pin data transfer rate. The module marked as HMCA8GR8MJR4C-EB carries 20 memory chips marked as H5CNAG4NMJ as well as IDT’s P8900-Z2 register clock driver (RCD). The memory devices are marked differently than the ones SK Hynix used for 16 GB RDIMM back in late 2018, though we do not know the difference.

The DDR5 RDIMMS feature 288 pins on a slightly curved edge connector (to reduce the insertion force on every pin), just like DDR4 modules, yet its layout and design are a bit different when compared to DDR4 to prevent installment of DDR5 modules into DDR4 slots and vice versa.

It is unknown whether SK Hynix has already started to sample its DDR5 RDIMMs with developers of server platforms and servers, but it is obvious that all DRAM makers are aligning their DDR5 production schedules with CPU designers and other companies.

At present, it is unclear when exactly the first DDR5 platforms are set to hit the market, but a good guess would be 2021. One of the first platforms to confirm support for DDR5 memory has been Intel's Xeon Sapphire Rapids, set for deployment in the Aurora Supercomputer. AMD support for DDR5 is unknown so far.

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Source: SK Hynix



View All Comments

  • Destoya - Monday, January 13, 2020 - link

    It always seems sort of pointless at the beginning of memory generations but performance and cost significantly improve over time. DDR4 launched at 2400/2666 and was very expensive compared to DDR3; I paid over $300 for 16GB of 2666C16 when it was new on the market. Reply
  • Alexvrb - Monday, January 13, 2020 - link

    ...what? First of all, 3200 is absolutely part of spec. Second, you absolutely SHOULD compare spec to spec. Second, they're talking about 4266-6400 for JEDEC DDR5. That's a huge leap when you actually compare apples-to-apples, and I imagine we'll see non-spec modules MUCH faster. There are other improvements too.

  • npz - Tuesday, January 14, 2020 - link

    Well I just found out that DDR4 - Unbuffered @ 3200 was only very recently approved in Aug 2019
    So that's why there aren't any on the market yet that's not XMP based, nor any ECC unbufferred at 3200

    And previously before that, Registered DIMMs (the high density server DIMMs) were only approved Mar 2019
  • antonkochubey - Tuesday, January 14, 2020 - link

    JEDEC-spec DDR4-3200 kits have existed for quite a while, e.g. Crucial CT16G4DFD832A was released back in April 2019. Reply
  • eek2121 - Monday, January 13, 2020 - link

    It's a bigger step up than you realize: DDR5 DIMMs are actually dual channel (per module). Reply
  • antonkochubey - Tuesday, January 14, 2020 - link

    Dual 32-bit channel, while DDR4 was single 64-bit channel. So total bus width is still the same, although random access to separate 'halves' of the module can be up to 2x faster in perfect conditions. Reply
  • Rudde - Tuesday, January 14, 2020 - link

    Isn't it dual 40 bit channel? Reply
  • Mugur - Tuesday, January 14, 2020 - link

    For ECC only. Reply
  • The_Assimilator - Tuesday, January 14, 2020 - link

    This engineering sample module is literally clocked more than twice the speed of launch-day DDR4 which was at 2133 MT/s... Reply
  • Santoval - Monday, January 13, 2020 - link

    "AMD support for DDR5 is unknown so far."
    While it is still unknown, the best guess would be 2021 as well. Zen 3 will apparently be the last AM4 socket Ryzen, and will be released in mid-late 2020. To support DDR5 AMD almost certainly need to change the CPU socket, and 2020 is too early anyway. So that leaves Zen 4 based Ryzen CPUs, which will require a new socket that will also support DDR5.

    One either option is early DDR5 support just for Zen 3 based Epyc server CPUs. Since AMD moved the DRAM controllers to an I/O die perhaps they could do that without requiring new chiplets just for Epyc. The problem AMD has with their server line is that they keep increasing the number of cores but the memory controllers have been limited to 8, so with each generation more cores compete for the same memory access.

    If they increase the cores of Zen 3 based Epyc CPUs further without DDR5 they might need to increase the memory channels to 12, and I doubt they would do that for just one server generation. So a way out would be early DDR5 support. Or no core increase. Q3/Q4 2020 might be too early for DDR5, even for servers. So they will either opt for no core increase or add one more chiplet pair for 80 cores while increasing the L3 cache and the supported DDR4 frequency further to compensate.

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