Micron announced at CES that it had started sampling of its DDR5 Registered DIMMs with select partners. The very fact that Micron started sampling of DDR5 modules indicates that its partners already have server CPUs/platforms that support DDR5 memory.

Micron expects its first-generation DDR5 products to offer ‘more than’ 1.85-times performance increase when compared to JEDEC-standard DDR4 memory. There are multiple improvements to DDR5 because in addition to data transfer rates of up to 6400 MT/s, DDR5 also has improved functionality. Firstly, DDR5 uses two independent 32/40-bit channels per module (without/or with ECC), which improves channel utilization. Also, DDR5 has an improved command bus efficiency because the channels feature their own 7-bit Address (Add)/Command (Cmd) buses, better refresh schemes, and an increased bank group for extra performance.

What is important is that the DDR5 specification allows to design chips with capacities higher than 16 Gb and reduce supply voltage to 1.1 V and an allowable fluctuation range of 3% (i.e., at ±0.033V). So, in addition to performance, DDR5 will enable to reduce power consumption and build servers featuring higher memory capacity.

Increasing usable memory bandwidth and capacity is crucially important for next-generation server platforms that use processors with even higher number of cores.

Micron did not reveal specifications of its DDR5 RDIMMs it sent to partners or disclose when it plans to start commercial shipments of DDR5 memory. We can speculate that DDR5-enabled server platforms are several quarters away, but it is up for actual platform developers to set launch dates.

Tom Eby, senior vice president and general manager of the Compute & Networking Business Unit at Micron, said the following:

“Data center workloads will be increasingly challenged to extract value from the accelerating growth of data across virtually all applications. The key to enabling these workloads is higher-performance, denser, higher-quality memory. Micron’s sampling of DDR5 RDIMMs represents a significant milestone, bringing the industry one step closer to unlocking the value in next-generation data-centric applications.”

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Source: Micron

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  • DanNeely - Tuesday, January 7, 2020 - link

    I'd love to see BW vs Core count graphs for non-server platforms (HEDT, mainstream desktop, laptop, mobile) too. Reply
  • Chaitanya - Tuesday, January 7, 2020 - link

    Isnt DDR5 offering capacity bump rather than speed? Reply
  • Yojimbo - Tuesday, January 7, 2020 - link

    That would really suck. As compute increases it needs more bandwidth. Reply
  • DanNeely - Tuesday, January 7, 2020 - link

    Sort of.

    On the PC a DDR5 dimm will offer 2 independent 32 bit channels instead of 1x64bit, but because the channel speed is nominally doubled each will be as fast as a DDR4 dimm. The reason it's being split into two independent channels is because more independent channels plays nicer with high core count systems.

    So while it won't help naively designed sequential access memory bound single threaded code much if at all overall multi-threaded performance should go up in memory bound cases.
    Reply
  • TomWomack - Tuesday, January 7, 2020 - link

    I didn't realise there were server platforms with DDR5 even on the drawing board; I suppose it's not a huge leap for AMD to make with their separate memory controller, and AMD were happy to be first to PCIe4.

    Ah, there are leaks suggesting this is Intel Sapphire Rapids (the second 10nm Xeon)
    Reply
  • DanNeely - Tuesday, January 7, 2020 - link

    It could be for ASIC/FPGA platforms not mainstream systems. Reply

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