Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s 7 nm process technology, and is designed to enable SoC developers to begin on their DDR5 memory subsystems now and get them to market in 2019-2020, depending on high-volume DDR5 availability. At a special event, Cadence teamed up with Micron to demonstrate their DDR5 DRAM subsystem. In the meantime, Micron has started to sample its preliminary DDR5 chips to interested parties. DDR5-4400 Initially, DDR5-6400 Eventually Cadence’s DDR5 memory controller and PHY achieve a 4400 MT/s data rate with CL42 using Micron’s prototype 8 Gb DDR5 memory chips. Compared to DDR4 today, the supply voltage of DDR5 is...
Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die...24 by Anton Shilov on 12/20/2017
JEDEC made two important announcements about the future of DRAM and non-volatile DIMMs for servers last week. Development of both is proceeding as planned and JEDEC intends to preview...38 by Anton Shilov on 4/3/2017