SK Hynix this week revealed some additional technical details about its upcoming DDR5-6400 memory chip at the International Solid State Circuits Conference. The die size of the company’s 16 Gb DDR5 chip is at a high end of historical DRAM die sizes, so the cost of the device will likely be quite high. However, the increased DRAM density per square millimeter will likely enable SK Hynix to build rather cost effective 8 Gb DDR5 ICs.
SK Hynix on Thursday announced that it had completed development of its first DDR5 memory chip. The new chip offers a capacity of 16 Gb and is said to...29 by Anton Shilov on 11/15/2018
The U.S. Department of Commerce this week banned U.S. exports to a China-based maker of DRAM. The DoC believes that Fujian Jinhua Integrated Circuit Company (also known as Fujian...58 by Anton Shilov on 11/1/2018
Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...18 by Anton Shilov on 10/17/2018
Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...31 by Anton Shilov on 5/3/2018
Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die...24 by Anton Shilov on 12/20/2017
JEDEC made two important announcements about the future of DRAM and non-volatile DIMMs for servers last week. Development of both is proceeding as planned and JEDEC intends to preview...38 by Anton Shilov on 4/3/2017