DDR5

SK Hynix on Thursday announced that it had completed development of its first DDR5 memory chip. The new chip offers a capacity of 16 Gb and is said to be the industry’s first DRAM that is fully compliant with the JEDEC standard, which is yet to be published. Meanwhile, mass production of SK Hynix's DDR5 memory chips is slated for 2020. The new DDR5 chip from SK Hynix supports a 5200 MT/sec/pin data transfer rate, which is 60% faster than the 3200 MT/s rate officially supported by DDR4. Meanwhile the DRAM operates at 1.1 Volts, a 9% decrease in operating voltage. The monolithic 16 Gb chip is made using SK Hynix’s second generation 10 nm-class process technology (also known as 1Ynm), though the company does...

U.S. Government Indicts Chinese DRAM Maker JHICC on Industrial Espionage; Bans Exports To Firm

The U.S. Department of Commerce this week banned U.S. exports to a China-based maker of DRAM. The DoC believes that Fujian Jinhua Integrated Circuit Company (also known as Fujian...

57 by Anton Shilov on 11/1/2018

Cadence & Micron DDR5 Update: 16 Gb Chips on Track for 2019

Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...

18 by Anton Shilov on 10/17/2018

Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019

Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...

31 by Anton Shilov on 5/3/2018

Samsung Starts Production of 8 Gb DDR4-3600 ICs Using 2nd Gen 10nm-Class Tech

Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die...

24 by Anton Shilov on 12/20/2017

JEDEC: DDR5 to Double Bandwidth Over DDR4, NVDIMM-P Specification Due Next Year

JEDEC made two important announcements about the future of DRAM and non-volatile DIMMs for servers last week. Development of both is proceeding as planned and JEDEC intends to preview...

38 by Anton Shilov on 4/3/2017

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