At Intel's Investor Day today, CEO Bob Swan and Murthy Renduchintala spoke to the ability of the company with respect to its manufacturing capabilities. Intel has historically been strong in its ability to execute on its process technology, however the delay of its 10nm process has obviously raised multiple question marks, and has done for several years. The two Intel executives went into a little detail about what Intel was doing in the interim, and how it has learned from the issues.

Back in 2013, Intel envisoned its 10nm to succeed the 14nm by providing 2.7x density, with new technologies such as Self-Aligned Quad Patterning (SAQP), Contact over Active Gate (COAG), Cobolt Interconnects, and new packaging technologies such as EMIB and Foveros. Intel admits that this was an ambitious plan, and the goals were not clearly defined with the teams and it was ultimately overly complex and not managed in an ideal way.

This ended up pushing 10nm out into a later time frame. In this case, Intel pushed 10nm out to 2019 (technically they shipped Cannon Lake in small quantities on 10nm in 2017, however that is nothing more than a curio in the timeline of semiconductors), and filled the gap with 14+ and 14++.

Intels 14+ and 14++ processes extracted more than 20% more performance (from Broadwell to Whiskey Lake) from the process since its inception. As a result, Intel is prepared to not only get ready for future intra-node optimizations, but actually adjust the roadmap to compensate for it. Murthy made it clear that Intel wants to introduce a Moore's Law-like gain at the beginning of a new process, and another similar gain by the end of the process.

Intel has stated that its 10nm product family (beyond Cannon Lake) will start to be available from the middle of this year (2019), with Ice Lake on client platforms (notebooks).

Intel will be launching multiple 10nm products through 2019 and 2020, including server based 10nm in the first half of 2020:

In the above slide, Intel states that it will have 7nm in production and launching a product in 2021. That sounds very aggressive for a company that has had issues with 10nm. It even shows in Intels radmap, with 10nm (and 10+ and 10++) having a much shorter life cycle than the 14nm family of processes.

With this in mind, Intel's 7nm is going to be the combination of what Intel has learned from the 14nm and 10nm family of products. Intel wants that 2x scaling (Moores Law), but with intra-node optimations planned as part of the roadmap. Intel is also reducing its number of design rules, which should help with execution. 7nm will also be where Intel intersects with EUV, and also introduce next-gen Foveros and EMIB packainging.

Intel provided this slide, which shows a monolithic PC-Centric die with a multi-die Data-Centric chip built on both Foveros and EMIB. This corroborates our discussion with Intel's chiplet and packaging team, who also stated that we would see Foveros and EMIB on a combined product - specifically the GPU.

Intel announced that its lead 7nm product (lead = top, or lead = first?) would be its new GPGPU, built on the Xe graphics architecture. Intel has stated that its Xe product stack will feature two different microarchitectures from mobile client up to GPGPU, with one of those architectures called Arctic Sound - technically Intel will launch its first discrete GPU in 2020 according to its press release, however the 7nm GPGPU will be launched in 2021.

More information is coming out of Intel's Event, more to follow.

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Source: Intel

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  • Nimrael - Thursday, May 09, 2019 - link

    What a BS... You wrote a some numbers and do not understand it's meaning.
    First of all, you compare HD cells of mobile chip with HP or even uHP cells of desktop dies.
    Secondary, TSMC's "5nm" in fact are no 5nm. Even not taking into the consideration that ASML NXE 3400B has a resolution of 13nm (and no 3400C has been shipped), 5nm (real, not PR) require scanner with the NA (mumerical aperture) of 0.5-0.6 instead of 3400B's 0.33
    Reply
  • Wilco1 - Thursday, May 09, 2019 - link

    Actually I do fully understand the meaning. TSMC server dies on 10nm (eg. Centriq) do achieve 3 times the density of current Intel 14nm servers. Future 10nm Intel servers will get at most 40 MT/mm^2, nowhere near the claimed 100 MT/mm^2. So while 7nm chips like Kirin 980 achieve close to 100MT/mm^2, the density claims from Intel are simply marketing bullshit.

    And nobody claimed that 5nm means exactly 5nm, the nm figure has not been accurate for more than a decade. It's simply a label which can be used as a density approximation.
    Reply
  • levizx - Friday, May 10, 2019 - link

    Actually NO, you DON'T understand what you are talking about. You are talking about ONE implementation of a specific process against a range of the other.
    Kirin 980 and A12 uses HD libs, Intel will not actually use those on their CPU, neither will AMD, so you are effectively comparing Intel 10nm with N7, when you should compare it to N7HPC. Radeon IV and Zen 2 both have MUCH lower density.
    Reply
  • Wilco1 - Friday, May 10, 2019 - link

    Actually I do. Intel will never release CPUs using their high density libraries so even talking about Intel high density libs is misleading, and using them for density comparisons is outright lying.

    Server chips made on TSMC (such as Centriq) are only 25% lower density than eg. Kirin 980. Zen 2 density figures should be available soon, I expect the density to be similar to Centriq since there will be a LOT of SRAM on the chiplet.
    Reply
  • Butterfish - Saturday, May 11, 2019 - link

    Centriq isn’t made by TSMC. It use Samsung’s 10nm Low Power Early library, and is only 20% denser than 14nm Skylake server chip despite Centriq using a low power high density library on “10nm” node Reply
  • Wilco1 - Saturday, May 11, 2019 - link

    Centriq is 3 times denser than 14nm Skylake, look up the numbers. Reply
  • levizx - Monday, May 13, 2019 - link

    Why are you fixating on hypothetical Centriq when Radeon IV and Ryzen is right in front of your eyes? You said yourself Intel will never use HD lib, then why do you bring up mobile SoC which IS on HD lib when you talk about density at all? Reply
  • levizx - Monday, May 13, 2019 - link

    In other words, Intel CPU's density is a design choice, not a process feature. You'll expect much higher density with Intel's FPGA IoT and GPU chips. Reply
  • Gondalf - Friday, May 10, 2019 - link

    Don't be a kid Wilco but try to have some proof about silicon manufacturing.
    You know that a server SKU can not be dense like a phone SOC, instead of the
    power density on die will not allow Intel to respect golden standards of long term reliability that
    OEMs ask.
    Bet Zen 2 core is not dense like TSMC claims about 7nm?? Bet actual Zen main defect is in
    dense library? This avoid to achieve high clock speeds on 14nm and this was the main reason
    of the very little success of actual Epyc.
    Try to be smart please. One thing is a very low power SOC, another story an high power SKU.
    Reply
  • Wilco1 - Friday, May 10, 2019 - link

    Seriously, is Centriq not a high performance high power server CPU??? Reply

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