Not Everyone Needs Leading Edge: TSMC’s 22 nm ULP, 12 nm FFC and 12 nm FFC+

Now let’s discuss something less advanced, but what is required for hundreds of millions of devices sold every year.

Advertised PPA Improvements of TSMC's Low-Power/Compact Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  CLN28HPC
vs
CLN28HPM
CLN28HPC+
vs
CLN28HPM
CLN22LPU
vs
CLNHPC+
CLN16FFC
vs
CLN16FF
CLN12FFC
vs
CLN16FFC
12FFC-ULP
vs
CLN12FFC
Power 20% 30% 35% lower 25% lower
Performance - 15% 15% unknown 10% unknown
Area Reduction 10% 10% 10% optional 20% unknown
HVM Start started started 2018 Q1 2016 2018 2019
Note Planar
28 nm-based
FinFET
16/20 nm-based

Development of FinFET-based chips is more expensive of ICs featuring planar transistors and their manufacturing is more costly as well. As a result, FinFET is virtually unavailable for many smaller designers of SoCs that usually build various solutions for emerging IoT applications. GlobalFoundries and Samsung offer their FD-SOI manufacturing processes to such companies (and these technologies have a number of other advantages in addition to being more cost-effective), whereas TSMC intends to introduce its new 22 nm ULP technology aimed at such applications. The CLN22ULP is an optimized version of the company’s 28 nm HPC+ (high-performance compact plus) manufacturing process that has been available for a while. The 22ULP offers a 10% area reduction and either a 15% performance improvement over the 28HPC+ process, or a 35% power drop. The 22ULP process joins a family of other ultra-low-power processes offered by TSMC and will compete against GlobalFoundries 22FDX as well as Samsung’s 28 nm FD-SOI offering.

Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity. Further down the road, TSMC also plans to offer a ULP version of the CLN12FFC with reduced voltage, but that is going to happen only in 2018 or 2019.

Sources: Samsung, TSMC, SemiWiki (123).

Related Reading:

Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • melgross - Saturday, May 6, 2017 - link

    A lot of chip experts don't believe that a true 5nm is possible. Not because we can't build it, but because the laws of physics are closing in. At that point, we have no substitute for FinFET, which doesn't work below 7 nm, and the three technologies that have been considered as a replacement aren't working either.

    When you begin to have features that are just 10 to 12 atoms wide, Heisenberg's Law hits you hard. As many electrons that travel through the feature, escape it. That's a death hell. So I expect that 7nm will really be 10 to 14 for most fabs, the way 14 is really 16 to 20 for most now.

    The next step is expected to be carbon nanotubes, which both Hp and ibm have been working for years, and have shown limited success. That hoped to be ready, in limited complexity, by 2005 to 2030.

    But there will be a wide gap between any silicon technology and that, even assuming they can get it working on a commercial basis at all. There are still too many steps for that, and they don't yet know how to climb them, or even if they're there.
    Reply
  • melgross - Saturday, May 6, 2017 - link

    Oops, too many typos. I meant, ready by 2025 to 2030, of course. Reply
  • Meteor2 - Sunday, May 7, 2017 - link

    You're right, but I think between EUV and further development of the new gate concepts we'll make 5 nm happen. Although as really it's a question of whether commercial interests will fund the R&D, rather can 'science' make it happen, I suppose there's a risk 5 nm won't happen as designing such chips will be fantastically expensive. Will we be prepared to spend the $$$ for the performance which would be delivered? Reply
  • lefty2 - Friday, May 5, 2017 - link

    Intel already has lost it's process advantage. Samsung's 10nm is currently in HVM and denser than Intel's 14nm. Intel say they will launch 10nm in 2017, but the yields are so bad they can hardly be considered production yield. By the time it reaches production yield TSMC will have 7nm Reply
  • Drumsticks - Friday, May 5, 2017 - link

    Intel's 10nm is going to be denser than Samsung or TSMC's 7nm imo, going by the numbers we see here. Intel's 14nm is already denser than their competition by somewhere in the realm of 30% (per the hard numbers Intel released a few weeks back, and nobody has contradicted them). Intel's jump to 10nm is going to provide ~2.7x higher density than their 14nm node, and I think they've said several times they plan to ship 10nm this year.

    Even with a 70% area reduction on 7nm vs 16nm at TSMC, I don't think that overcomes a 30% lead + a 2.7x increase in density on top of that lead.

    For another comparison, Intel's 10nm measures 100M transistors / mm^2, versus their competition at 50M / mm^2 at 10nm. Assuming TSMC's transistor density is around the "Others" metric, a 37% reduction in area from 10nm to 7nm would still leave them short of Intel's process node. I suspect everybody else will need a 5nm node to temporarily jump ahead of Intel's 10nm, before Intel's 7nm rolls around in 2020 or something and puts everybody behind again.

    Numbers come from https://newsroom.intel.com/newsroom/wp-content/upl... which based on most of what I've seen has been accepted as a well done report. I'd love to see everybody switch to a more objective metric, since process node is now just a marketing game.
    Reply
  • vladx - Friday, May 5, 2017 - link

    They obviously can't compete with Intel head-to-head so say they have to resort to marketing gimmicks to make it appear they're coming ahead. Reply
  • SuperMecha - Saturday, May 6, 2017 - link

    Intel's 14nm density advantage compared to GF/Samsung's 14nm process is only 23% not 30%. Also Intel's recent presentation only compares up to their competitor's 10nm not 7nm. In 2018 Intel will lose it transistor density advantage.

    https://www.semiwiki.com/forum/content/6713-14nm-1...
    Reply
  • Drumsticks - Saturday, May 6, 2017 - link

    I know Intel compared to the 10nm products; I was just extrapolating from that based on what TSMC stated (in the article) about their 7nm vs their own 16nm and 10nm. With everybody using different statistics now for each of their parts, it's not surprising that Intel gets passed every now and then, considering the time between their nodes is getting longer and longer. Reply
  • lefty2 - Saturday, May 6, 2017 - link

    Scotten Jones did a detailed analysis of various leading edge nodes and concluded that TSMC's 7nm is slightly denser than Intel's 10nm and Samsun/TSMC 10nm is slightly desnser than Intel's 14nm:
    https://www.semiwiki.com/forum/content/6713-14nm-1...
    Intel's 2017 launch of 10nm is virtually a paper launch. They are only going to release a couple of low volume SKUs at the very end of 2017, just so they can claim that they have the process lead. It's not till late 2018, or 2019 that the bulk of their products go to 10nm. Also the first iteration of 10nm performs worse than Intel's current 14nm+ process.
    Reply
  • melgross - Saturday, May 6, 2017 - link

    I don't believe it. First of all, neither he, or anyone else outside those companies actually knows enough about the actual chips to know the true density. Evaluating these by making some basic mathematical calculations doesn't tell us anything about the actual processes. It's all theoretical. Reply

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