Interconnect

With the battleground moving from single core performance to multi-core acceleration, a new war is being fought with how data is moved around between different compute resources. The Interconnect Wars are truly here, and the battleground just got a lot more complicated. We’ve seen NVLink, CCIX, and GenZ come out in recent years as offering the next generation of host-to-device and device-to-device high-speed interconnect, with a variety of different features. Now CXL, or Compute Express Link, is taking to the field.

Gen-Z Interconnect Core Specification 1.0 Published

The first major release of the Gen-Z systems interconnect specification is now available. The Gen-Z Consortium was publicly announced in late 2016 and has been developing the technology as...

23 by Billy Tallis on 2/13/2018

Gen-Z Consortium Formed: Developing a New Memory Interconnect

Anyone tasked with handling the way data is moved around a processor deserves praise. It takes time, dedication and skill to design something that not only works appropriately and...

15 by Ian Cutress on 10/12/2016

Arteris Announces Ncore Cache-Coherent Interconnect

Arteris is a little mentioned company which we haven't had the opportunity to cover in the past, yet they provide IP for one of the most important parts of...

9 by Andrei Frumusanu on 5/24/2016

ARM Announces New CCI-550 and DMC-500 System IPs

Today ARM announces two new additions to its CoreLink system IP design portfolio, the CCI-550 interconnect and DMC-500 memory controller. Starting off with the CCI announcement, we find the...

5 by Andrei Frumusanu on 10/27/2015

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