On the back of Intel’s Technology and Manufacturing Day in March, the company presented another iteration of the information at an equivalent event in Beijing this week. Most of the content was fairly similar to the previous TMD, with a few further insights into how some of the technology is progressing. High up on that list would be how Intel is coming along with its own 10nm process, as well as several plans regarding the 10nm product portfolio.

The headline here was ‘we have a wafer’, as shown in the image above. Intel disclosed that this wafer was from a production run of a 10nm test chip containing ARM Cortex A75 cores, implemented with ‘industry standard design flows’, and was built to target a performance level in excess of 3 GHz. Both TSMC and Samsung are shipping their versions of their ‘10nm’ processes, however Intel reiterated the claim that their technology uses tighter transistors and metal pitches for almost double the density of other competing 10nm technologies. While chips such as the Huawei Kirin 970 from TSMC’s 10nm are in the region of 55 million transistors per mm2, Intel is quoting over 100 million per mm2 with their 10nm (and using a new transistor counting methodology).

Intel quoted a 25% better performance and 45% lower power than 14nm, though failed to declare if that was 14nm, 14+, or 14++. Intel also stated that the optimized version of 10nm, 10++, will boost performance 15% or reduce power by 30% from 10nm. Intel’s Custom Foundry business, which will start on 10nm, is offering customers two design platforms on the new technology: 10GP (general purpose) and 10HPM (high performance mobile), with validated IP portfolios to include ARM libraries and POP kits and turnkey services. Intel has yet to announce a major partner in its custom foundry business, and other media outlets are reporting that some major partners that had signed up are now looking elsewhere.

Earlier this year Intel stated that its own first 10nm products would be aiming at the data center first (it has since been clarified that Intel was discussing 10nm++). At the time it was a little confusing, given Intel’s delayed cadence with typical data center products. However, since Intel acquired Altera, it seems appropriate that FPGAs would be the perfect fit here. Large-scale FPGAs, due to their regular repeating units, can take advantage of the smaller manufacturing process and still return reasonable yields by disabling individual gate arrays with defects and appropriate binning. Intel’s next generation of FPGAs will use 10nm, and they will go by the codename “Falcon Mesa”.

Falcon Mesa will encompass multiple technologies, most noticeably Intel’s second generation of their Embedded Multi-Die Interconnect Bridge (EMIB) packaging. This technology embeds the package with additional silicon substrates, providing a connection between separate active silicon parts much faster than standard packaging methods and much cheaper than using full-blown interposers. The result is a monolithic FPGA in the package, surrounded by memory or IP blocks, perhaps created at a different process node, but all using high-bandwidth EMIB for communication. On a similar theme, Falcon Mesa will also include support for next-generation HBM.


Possibilities with EMIB

Among the IP blocks that can be embedded via EMIB with the new FPGAs, Intel lists both 112 Gbps serial transceiver links as well as PCIe 4.0 x16 connectivity, with support for data rates up to 16 GT/s per lane for future data center connectivity. This was discussed at the recent Hot Chips conference, in a talk I’d like to get some time to expand in a written piece.

No additional information was released regarding 10nm products for consumer devices.

Related Reading

Additional: 1:00pm September 19th

After doing some digging, we have come across several shots of the wafer up close.


From http://news.mydrivers.com/

This is from the presentational display. Detail is very hard to make out at the highest resolution we can find this image.

Additional: 1:20pm September 19th

Intel has also now put the presentation up on the website, which gives us this close-up:

Surprisingly, this wafer looks completely bare. Either this is simply a 300mm wafer before production, or Intel have covered the wafer on purpose with a reflective material to stop prying eyes. It's a very odd series of events, as Intel did have other wafers at the event, including 10nm using ARM, and examples of the new 22FFL process.


From http://news.mydrivers.com/

From http://news.mydrivers.com/

Both of these wafers seem to have a repeating pattern we would typically see on a manufactured wafer. So either Intel does not want anyone to look at 10nm Cannon Lake just yet, or they were just holding up an unused disc of silicon.

Additional: 3:00pm September 20th

Intel got back to us with a more detailed Cannon Lake image, clearly showing the separate dies:

Manual counting puts the wafer at around 36 dies across and 35 dies down, which leads to a die size of around 8.2 mm by 8.6 mm, or ~70.5 mm2 per die. At that size, it would suggest we are likely looking at a base dual-core die with graphics: Intel's first 14nm chips in a 2+2 configuration, Broadwell-U, were 82 mm2, so it is likely that we are seeing a 2+2 configuration as well. At that size, we're looking at around 850 dies per wafer.

Source: Intel

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  • MajGenRelativity - Tuesday, September 19, 2017 - link

    Looks interesting. I hope we'll see 10nm in consumer devices within a couple years Reply
  • SharpEars - Tuesday, September 19, 2017 - link

    I hope we'll see some FPGA goodness in consumer devices in a couple years. Reply
  • MajGenRelativity - Tuesday, September 19, 2017 - link

    What would they be used for? Reply
  • ddriver - Tuesday, September 19, 2017 - link

    More of that "inferior glue" LOL Reply
  • MajGenRelativity - Tuesday, September 19, 2017 - link

    That does not answer my question, as your answer doesn't make any sense. Reply
  • wumpus - Tuesday, September 19, 2017 - link

    It makes sense assuming that there really isn't much reason to put FPGA code in a high volume processor. Of course with this interconnect, it hardly has to be all *that* high volume, but it is still there.

    Crytography/cryptomining is really the only thing I'd expect to see FPGAs do anything in/near a CPU. I'd be a lot more interested if there were some sort of FPGA-based GPU operations, they typically have the wide operations, latency/pipelining, and bandwidth to make FPGA operations really shine. They also have those "one or two little operations" that are optimized to extreme levels.
    Reply
  • Notmyusualid - Tuesday, September 19, 2017 - link

    @ wumpus

    Nope - The FPGAs can be used to support often-used code, that typically takes much CPU time to do. There is a good write up on it over on IEEE. They 'hard coded' the FPGAs to do these repeatable, but necessary tasks, which were done much quicker than the CPU would normally be capable of - and they got wonderful overall performance gains by doing so.

    I don't think anyone on that project gave a toss about crypto mining. They were trying to accelerate everyday software.
    Reply
  • Notmyusualid - Tuesday, September 19, 2017 - link

    @ MajGen

    You will come learn ddriver is the local clown here. Try to ignore, if you can.
    Reply
  • MajGenRelativity - Tuesday, September 19, 2017 - link

    I'm aware :P In any case, I liked your point about the FPGA accelerating everyday software. Reply
  • HStewart - Tuesday, September 19, 2017 - link

    It obvious we need some explanation of what FPGA is and it definitely not glue.

    https://en.wikipedia.org/wiki/Field-programmable_g...

    this technology is typically use to make custom design chips - which can be program from outside.
    Reply

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