One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:

As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:

This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.

Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.

TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.

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  • Ian Cutress - Tuesday, August 25, 2020 - link

    The problem started when customers were using N7+ to mean 'beyond 7nm but still on DUV', which was then called N7P (or perhaps just enhanced versions of N7).

    N7+ is very specifically the EUV version of N7.
    Reply
  • smalM - Wednesday, August 26, 2020 - link

    Au contraire, N7+ is very specifically not the EUV version of N7 (that's N6).

    You are Ian Cutress so you have to weigh your words ;-)
    Reply
  • Grayson Carlyle - Wednesday, August 26, 2020 - link

    Did you even attempt to look anything up before you stated something wrong? Reply
  • Spunjji - Thursday, August 27, 2020 - link

    It baffles me how some people will talk nonsense with such confidence Reply
  • Wilco1 - Thursday, August 27, 2020 - link

    To be fair I think he isn't saying that N7+ isn't EUV but that it is not compatible with N7, while N6 provides an almost seamless upgrade from N7 with the same benefits as N7+. So it's more correct to say that N6 is the EUV version of N7. Reply
  • smalM - Saturday, August 29, 2020 - link

    It baffles me, that people don't read the exact words in a post about using words exactly. Reply
  • willgart - Tuesday, August 25, 2020 - link

    at the same time at Intel:
    yes! we are on track ... we are 6months late for our 7nm process!
    Reply
  • FreckledTrout - Tuesday, August 25, 2020 - link

    Which lands Intel over 1 year after TSMC's 5nm which likely will be very similar to Intel's 7nm node. Reply
  • FreckledTrout - Tuesday, August 25, 2020 - link

    (I should have noted TSMC's 5nm high performance used for AMD chips not he Initial low power 5nm for say Apple SoC's.) Reply
  • edzieba - Tuesday, August 25, 2020 - link

    For comparison: TSMC announced 7nm in 2015, announced production start in April 2017, and the Ryzen 3xxx series arrived July 2019. Reply

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