N7

One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process. The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per...

TSMC Radically Boosts CapEx to Expand Production Capacities, To Reach $14B For 2019

Forecasting strong demand for its 5 nm and 7 nm class process technologies in the coming years, TSMC has announced that it's increasing its capital expenditure for 2019 by...

18 by Anton Shilov on 10/18/2019

Samsung & TSMC Develop 8nm & 7nm Automotive-Grade Nodes

As vehicles are getting ‘smarter’ and gaining autopilot capabilities, it is easy to predict that the demand for higher-performing and more complex automotive SoCs will be growing rapidly in...

29 by Anton Shilov on 10/14/2019

TSMC: N7+ EUV Process Technology in High Volume, 6nm (N6) Coming Soon

TSMC announced on Monday that its customers have started shipping products based on chips made by TSMC using its N7+ (2nd Generation 7 nm with EUV) process technology that...

27 by Anton Shilov on 10/8/2019

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