Floating Point

The key highlight improvement for floating point performance is full AVX2 support. AMD has increased the execution unit width from 128-bit to 256-bit, allowing for single-cycle AVX2 calculations, rather than cracking the calculation into two instructions and two cycles. This is enhanced by giving 256-bit loads and stores, so the FMA units can be continuously fed. AMD states that due to its energy aware scheduling, there is no predefined frequency drop when using AVX2 instructions (however frequency may be reduced dependent on temperature and voltage requirements, but that’s automatic regardless of instructions used)

In the floating point unit, the queues accept up to four micro-ops per cycle from the dispatch unit which feed into a 160-entry physical register file. This moves into four execution units, which can be fed with 256b data in the load and store mechanism.

Other tweaks have been made to the FMA units than beyond doubling the size – AMD states that they have increased raw performance in memory allocations, for repetitive physics calculations, and certain audio processing techniques.

Another key update is decreasing the FP multiplication latency from 4 cycles to 3 cycles. That is quite a significant improvement. AMD has stated that it is keeping a lot of the detail under wraps, as it wants to present it at Hot Chips is August. We’ll be running a full instruction analysis for our reviews on July 7th.

Decode Integer Units, Load and Store
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  • fmcjw - Tuesday, June 11, 2019 - link

    All good and fine, but I want Zen 2 and 7nm on my laptop. If they aren't announcing it today, products aren't gonna ship by holiday 2019, and most consumers will end up buying 10nm Intel devices. Missed chance.
  • mode_13h - Tuesday, June 11, 2019 - link

    Eh, they have perfectly good 12 nm laptop SoCs. 7 nm would've been nice, but it's hard to do everything at once.
  • levizx - Tuesday, June 11, 2019 - link

    Nope, those 12nm APUs have worse battery life (than current 8th Gen) and no TB3/USB4 support. I can't think of a reason where I would choose Ryzen 3xxxU over Ice Lake
  • mode_13h - Tuesday, June 11, 2019 - link

    Do price & availability count?
  • Xyler94 - Tuesday, June 11, 2019 - link

    Misleading remarks. Huawei was able to make a Ryzen APU have better battery life than an 8th gen processor. TB3 and USB4 aren't readily used mainstream yet. Heck USB-C hasn't even caught on yet.

    Currently laptop makers aren't optimizing AMD's CPU, that's just the fact.
  • Cooe - Wednesday, June 12, 2019 - link

    This is mostly nonsense. Performance AND battery life for Ryzen Mobile 2nd Gen is extremely close to Intel's current 8th & 9th gen 4-core parts. And until Ice Lake is a real thing that you can actually buy, Ryzen still has a major value advantage + far better iGPU performance. Ice Lake also isn't really any faster CPU wise than Whiskey Lake, because despite increasing IPC by +18%, clock-speeds were dropped from 4.8 to 4.1GHz, or about -16%, erasing nearly all those gains.
  • fmcjw - Tuesday, June 11, 2019 - link

    Yeah, I get that they still need time to get the GPU down to 7nm, so they pushed it back to focus on the CPU for desktop (where performance per watt matters much less than server or mobile). But the silence is not reassuring, and mobile-wise, Zen is still inferior to Intel, maybe not performance-wise as Huawei demonstrates with its Matebook, but definitely battery-wise because of the more powerful GPU.
  • scineram - Tuesday, June 11, 2019 - link

    Nobody is going to buy Shintel vaporware. Or only very few.
  • The_Assimilator - Tuesday, June 11, 2019 - link

    Please edit the table on page 1 to combine the rows with identical values into a single row (e.g. the RAM speed). Also edit the 3950X price to have a ? after it as it's not yet confirmed.
  • jfmonty2 - Tuesday, June 11, 2019 - link

    The 3950X price is most definitely confirmed; Lisa Su said it loud and clear (and showed it on the slide) in AMD's E3 presentation yesterday: https://www.youtube.com/watch?v=yxPBXNuX6Xs&t=...

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