Memory Subsystem: Bandwidth

Measuring the full bandwidth potential with John McCalpin's Stream bandwidth benchmark is getting increasingly difficult on the latest CPUs, as core and memory channel counts have continued to grow.  We compiled the stream 5.10 source code with the Intel compiler (icc) for linux version 17, or GCC 5.4, both 64-bit. The following compiler switches were used on icc:

icc -fast  -qopenmp  -parallel (-AVX) -DSTREAM_ARRAY_SIZE=800000000 

Notice that we had to increase the array significantly, to a data size of around 6 GB. We compiled one version with AVX and one without. 

The results are expressed in gigabytes per second.

Meanwhile the following compiler switches were used on gcc:

-Ofast -fopenmp -static -DSTREAM_ARRAY_SIZE=800000000

Notice that the DDR4 DRAM in the EPYC system ran at 2400 GT/s (8 channels), while the Intel system ran its DRAM at 2666 GT/s (6 channels). So the dual socket AMD system should theoretically get 307 GB per second (2.4 GT/s* 8 bytes per channel x 8 channels x 2 sockets). The Intel system has access to 256 GB per second (2.66 GT/s* 8 bytes per channel x 6 channels x 2 sockets).

Stream Triad (6 GB)

AMD told me they do not fully trust the results from the binaries compiled with ICC (and who can blame them?). Their own fully customized stream binary achieved 250 GB/s. Intel claims 199 GB/s for an AVX-512 optimized binary (Xeon E5-2699 v4: 128 GB/s with DDR-2400). Those kind of bandwidth numbers are only available to specially tuned AVX HPC binaries. 

Our numbers are much more realistic, and show that given enough threads, the 8 channels of DDR4 give the AMD EPYC server a 25% to 45% bandwidth advantage. This is less relevant in most server applications, but a nice bonus in many sparse matrix HPC applications. 

Maximum bandwidth is one thing, but that bandwidth must be available as soon as possible. To better understand the memory subsystem, we pinned the stream threads to different cores with numactl. 

Pinned Memory Bandwidth (in MB/sec)
Mem
Hierarchy
AMD "Naples"
EPYC 7601
DDR4-2400
Intel "Skylake-SP"
Xeon 8176
DDR4-2666
Intel "Broadwell-EP"
Xeon E5-2699v4
DDR4-2400
1 Thread 27490 12224 18555
2 Threads, same core
same socket
27663 14313 19043
2 Threads, different cores
same socket
29836 24462 37279
2 Threads, different socket 54997 24387 37333
4 threads on the first 4 cores
same socket
29201 47986 53983
8 threads on the first 8 cores
same socket
32703 77884 61450
8 threads on different dies 
(core 0,4,8,12...)
same socket
98747 77880 61504

The new Skylake-SP offers mediocre bandwidth to a single thread: only 12 GB/s is available despite the use of fast DDR-4 2666. The Broadwell-EP delivers 50% more bandwidth with slower DDR4-2400. It is clear that Skylake-SP needs more threads to get the most of its available memory bandwidth.

Meanwhile a single thread on a Naples core can get 27,5 GB/s if necessary. This is very promissing, as this means that a single-threaded phase in an HPC application will get abundant bandwidth and run as fast as possible. But the total bandwidth that one whole quad core CCX can command is only 30 GB/s.

Overall, memory bandwidth on Intel's Skylake-SP Xeon behaves more linearly than on AMD's EPYC. All off the Xeon's cores have access to all the memory channels, so bandwidth more directly increases with the number of threads. 

Testing Notes & Benchmark Configuration Memory Subsystem: Latency
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  • CajunArson - Tuesday, July 11, 2017 - link

    Would a high-end server that was built in 2014 necessarily update? Maybe not.

    Should a high-end server with a brand new microarchitecture use the most recent version of the software if it has any expectation of seeing a real benefit? Absolutely.

    If this was a GPU review and Anandtech used 2 year old drivers on a new GPU (assuming they even worked at all) we wouldn't even be having this conversation.
  • BrokenCrayons - Tuesday, July 11, 2017 - link

    Home users playing video games are in a different environment than you find in a business datacenter. There's a lot less money to be lost when a driver update causes a performance regression or eliminates a feature. Conversely, needlessly updating software in the aforementioned datacenter can result in the loss of many millions if something goes wrong.
  • wallysb01 - Tuesday, July 11, 2017 - link

    Conversely, having stuff working, but unnecessarily slowly costs money as well. Its a balance, and if you're spending hundreds of thousands or even millions on a cluster/data center/what have you, you'd probably want to spend at least a little bit of time optimizing it, right?
  • Icehawk - Tuesday, July 11, 2017 - link

    Most of the businesses I have worked for, ranging from 10 people to 50k, use severely outdated software and the barest minimum of patching. Optimization? HA!

    For example I work for a manufacturer & retailer currently, our POS system was last patched in 2012 by the vendor and has been replaced by at least two versions newer. We have XP machines in each of our stores as that is the only OS that can run the software.

    The above is very typical. The 50k company I worked for had software so old and deeply entrenched that modernizing it is virtually impossible. My current company is working on getting to a new product... that was new in 2012 and has also been replaced with a newer version. Whee!
  • Icehawk - Tuesday, July 11, 2017 - link

    One other thing - maybe the big shops actually do test/size but none of the places I have worked at and have been involved in do any testing, benchmarking, etc. They just buy whatever their preferred vendor gives them that meets the budget and they *think* will work. My coworker is in charge (lol) of selecting servers for a new office... he has no clue what anything in this article is. He has never read a single review, overview, or test of a processor. I could keep going on like this :(
  • 0ldman79 - Wednesday, July 12, 2017 - link

    Icehawk's comments are so accurate it is scary.

    I can't tell you how many businesses running custom *nix software running in a VM on a Windows server.

    They're not all about speed. Reliability is the single most important factor, speed is somewhere down the line. The people that make those decisions and the people that drink coffee while they're waiting on the machines are very different.

    Neither understand that it could all be done so much better and almost all of them are utterly terrified at the concept of speeding up the process if it means *any* changes are made.
  • JohanAnandtech - Friday, July 21, 2017 - link

    We did test with NAMD 2.12 (Dec 2016).
  • sutamatamasu - Tuesday, July 11, 2017 - link

    Glad, AMD make back again to this segment, now we can only see what can Raja to do for server market with Radeon instinct.
  • Kaotika - Tuesday, July 11, 2017 - link

    So this confirms that the previous information regarding Skylake-X core configurations was wrong, and 12-core variant is in fact using HCC-core instead of LCC-core?
  • Ian Cutress - Tuesday, July 11, 2017 - link

    We corrected that in our Skylake-X review.

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