Samsung and TSMC made several important announcements about the present and future of their semiconductor manufacturing technologies in March. Samsung revealed that it had shipped over 70 thousand wafers processed using its first-generation 10 nm FinFET fabrication process (10LPE) and also announced major additions to its upcoming manufacturing technology roadmap. In particular, the company plans to introduce three processes it has not talked about thus far. TSMC said that it is about to start mass production of ICs (integrated circuits) using its first-gen 10 nm technology and also announced several new processes that will be launched in the coming years, including its first 7 nm EUV process due in 2019.

10 nm: Samsung Is Shipping

Update 5/12: Samsung informed us that its press release from October, 2016, compares characteristics of the 10LPE manufacturing technology with those of the 14LPE, not 14LPP. The text and table have been updated accordingly.

Samsung said it had started to make SoCs using its 10LPE fabrication technology last October, which is something we already knew. This manufacturing process allowed the company to make its chips 30% smaller compared to ICs made using its 14LPE process as well as reducing power consumption by 40% (at the same frequency and complexity) or increase their frequency by 27% (at the same power and complexity). So far, Samsung has processed over 70 thousand wafers using its 10LPE technology, which can give an idea about Samsung’s 10 nm production capacities (considering that the whole 10 nm production cycle is greater than the 90 days we saw with previous-gen FinFET processes). At the same time, keep in mind that Samsung does not have many 10 nm designs to manufacture right now: we know only of the company’s own Exynos 9 Octa 8895 as well as Qualcomm’s Snapdragon 835 seen in the Samsung Galaxy S8.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  GF Samsung
7nm DUV
vs 14LPP
14LPP
vs 28LPP
10LPE
vs 14LPE
10LPE
vs 14LPP
10LPP
vs 10LPE
10LPU
vs
10LPE
Power >60% 60% 40% 30% ~15% ?
Performance >30% 40% 27% >10% ~10% ?
Area Reduction >50% 50% 30% 30% none ?

In addition to its production milestone, Samsung also confirmed plans to start mass production of chips using its second-generation 10 nm manufacturing process called 10LPP (10 nm low-power plus) by the end of 2017 as well as its third-generation 10 nm technology called 10LPU by the end of 2018. Samsung said last year that the 10LPP is going to enable a ~10% performance increase (at the same power and at the same complexity) versus the 10LPE, but we know absolutely nothing about the 10LPU. It is logical to assume that the 10LPU will bring certain PPA-related (performance, power, area) improvements, but it is not clear how Samsung plans to achieve them and which one of the three will be the focus for improvements. As it appears, just like Intel, Samsung has ended up with three generations of 14 nm fabrication processes and is going to end up with three generations of 10 nm manufacturing technologies. It is noteworthy that Samsung itself does not use its 14LPC (low-power compact) for its leading edge SoCs, which may suggest that the 10LPU is also not aimed at this segment of the market. In fact, it is highly likely that the 10LPU will target ultra-small and ultra-low-power ICs for various emerging devices, but Samsung yet has to confirm that.

10nm: TSMC Is Steady

As for TSMC, its 10 nm process technology (CLN10FF) is now qualified for production at the company’s GigaFabs 12 and 15, where high-volume ramp is expected to start in H2 2017. Production capacity of these two fabs is hundreds of thousands wafer starts per quarter and TSMC plans to ship 400 thousand wafers processed using its 10 nm manufacturing tech this year. Considering the long production cycles for FinFET-based technologies, it is about time for TSMC to start ramping up 10 nm so to be able to supply enough chips to its main customer in time. Apple is expected to launch its new iPhone products in September or October and needs to get SoCs couple of months before the launch.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  TSMC
16FF+
vs
28HPM
16FF+
vs
20SOC
10FF
vs
16FF+
7FF
vs
16FF+
7FF
vs
10FF
Power 70% 60% 40% 60% <40%
Performance 65% 40% 20% 30% ?
Area Reduction ~50% none >50% 70% >37%

PPA advantages of TSMC’s CLN10FF over its CLN16FF+ (second-gen 16 nm) have been discussed already and they are significant for developers of mobile SoCs (but not that significant for makers of other ICs): a ~50% higher transistor density, a 20% performance improvement at the same power and complexity or a 40% lower power consumption at the same frequency and complexity. Unlike Samsung, TSMC does not seem to plan multiple generations of 10 nm and will go straight to 7 nm next year. 7nm is currently very popular among chip designers, indicating a future major milestone. However, in addition to the CLN7FF, the company will also offer several other manufacturing technologies for ultra-small and ultra-low-power applications.

Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV
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  • Hulk - Friday, May 05, 2017 - link

    Yeah it's called "Assembly." We'll have come full circle. In the beginning it was assembly because processors were so slow. And it appears the end it will also be Assembly as processor power stalls. Kind of fitting. I used to program in Assembly on my Atari 800 back in 1982. Reply
  • vladx - Friday, May 05, 2017 - link

    Not sure if serious, Assembly can work for small to medium projects, but not really big ones. Reply
  • patrickjp93 - Friday, May 05, 2017 - link

    Roller Coaster Tycoon was programmed 100% in assembly, and that is not a medium-sized project. Reply
  • vladx - Friday, May 05, 2017 - link

    Only the first 2 RCT games were wwritten in assembly and both had only 2d graphics so it was mostly game logic which doesn't take much code. So yes, I would call that a mid-sized project. Reply
  • mapesdhs - Saturday, May 06, 2017 - link

    I once wrote an entire word processor in 68K, it worked very well (students ended up using it instead of the Uni-supplied program). People make false assumptions about coding in assembly. Beyond a certain point in complexity, its use becomes more like a high level language, ie. setting parameters and calling procedures & functions. Just the natural way one solves problems in a structured manner brings this about. Assembler doesn't inherantly lend itself to structured programming, but it doesn't have to; it's not hard to use it in a way that makes up for such issues, ie. a long as the design process itself is structured. I found it to be the best of both worlds, getting at the raw metal but also being able to focus on higher level design issues. Easily the most fun project I ever worked on, and the largest printed listing the uni in question had ever received at the time. :D (took 2.5 hours to print out) Reply
  • prisonerX - Sunday, May 07, 2017 - link

    Yeah, Roller Coaster Tycoon was written in 1999, nearly 20 years ago.

    Welcome to the 21st century, you might want to look around, some things have changed.
    Reply
  • prisonerX - Sunday, May 07, 2017 - link

    Uh, no. A compiler like GCC or LLVM will beat hand coded assembly every time on modern processors, without fail, unless you're talking about tiny or specialized code (say, bootloaders).

    The mistake you're making could be characterised as "premature optimisation" on a grand scale. You think if you tweak every bit of code and write it in assembly you'll get something more efficient. Sorry to break it to you, but you won't. Good structure (this includes choice of data structures and algorithms) is a greater influence on code than tweaking, if you're talking about anything of a reasonable and practical size.
    Reply
  • Kevin G - Sunday, May 07, 2017 - link

    The general rule of thumb is that hand coded assembly will be used in critical loops to accelerate portions of code that compilers like GCC or LLVM produce.

    You're not wrong about data structures and algorithm choice but in the light of smart decisions there, assembly is the next level of optimization. Assembler can't fix GIGO.
    Reply
  • amosbatto - Monday, May 21, 2018 - link

    I doubt that assembly will come into vogue, but a whole new generation of compiled languages are appearing which are designed for speed and low resource consumption: Rust, Julia, Swift, Go and NIM. These languages have performance which is slightly slower than C, but without its security problems, so I expect them to be widely used in the future as the hardware stops getting faster. Reply
  • Meteor2 - Friday, May 05, 2017 - link

    More to come from ISA developments, too. Maybe not huge amounts but definitely some -- SVE for example. Reply

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