Western Digital this week made three important announcements concerning its RISC-V-based processor initiative launched last year. The company introduced its own SweRV general-purpose core, its OmniXtend cache coherency over Ethernet technology, and the open-sourced SweRV Instruction Set Simulator (ISS). Western Digital expects that the hardware and software will be used for various solutions aimed at Big Data and Fast Data applications, including flash controllers and SSDs. Western Digital’s RISC-V SweRV core is a 32-bit in-order core featuring a 2-way superscalar design and a nine-stage pipeline. When implemented using a 28 nm process technology, the core runs at up to 1.8 GHz. As for simulated performance, the SweRV core delivers 4.9 CoreMark/MHz, which is a bit higher when compared to ARM’s Cortex-A15. Western Digital will use...
Apacer has announced a lineup of 32-bit SO-DIMMs designed for systems based on processors featuring Arm, RISC, or RISC-V architectures. The memory modules will enable SoC developers to take...5 by Anton Shilov on 11/26/2018
Western Digital recently announced plans to use the RISC-V ISA across its existing product stack as well as for future products that will combine processing and storage. The company...10 by Anton Shilov on 12/14/2017
SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which...9 by Anton Shilov on 7/18/2016