RISC-V

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth. The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company’s RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries’ 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices GloFo's advanced fab technology. GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and...

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year’s we’ve seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we’ve seen...

70 by Andrei Frumusanu on 10/30/2019

SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs

SiFive, one of the world’s leading developers of controllers and SoCs based on the RISC-V instruction set, has acquired USB IP portfolio from Innovative Logic, a silicon IP designer...

7 by Anton Shilov on 5/23/2019

Western Digital’s RISC-V "SweRV" Core Design Released For Free

Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as...

14 by Anton Shilov on 2/15/2019

Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative

Western Digital this week made three important announcements concerning its RISC-V-based processor initiative launched last year. The company introduced its own SweRV general-purpose core, its OmniXtend cache coherency over...

11 by Anton Shilov on 12/5/2018

Apacer Launches 32-Bit SODIMM for Arm & RISC-V Systems

Apacer has announced a lineup of 32-bit SO-DIMMs designed for systems based on processors featuring Arm, RISC, or RISC-V architectures. The memory modules will enable SoC developers to take...

5 by Anton Shilov on 11/26/2018

Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms

Western Digital recently announced plans to use the RISC-V ISA across its existing product stack as well as for future products that will combine processing and storage. The company...

10 by Anton Shilov on 12/14/2017

SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips

SiFive, a company established by researchers who invented the RISC-V instruction set architecture in the University of California Berkeley several years ago, has this week announced two platforms which...

9 by Anton Shilov on 7/18/2016

Log in

Don't have an account? Sign up now