Codename ManiaWe're about to get into a discussion of two new CPUs cores, both due in the 2009 time frame and we'd like to apologize in advance for the sheer number of code names that may be thrown at you. In the past two days we've heard AMD tell us about the following projects:
Many of these codenames refer to platforms including other codenames; understanding the architecture is honestly easier than understanding the nomenclature, which I believe is bad. We've done our best to organize it all in an easy to understand fashion, so please bear with us.
New CPUsAMD and Intel agree on a lot these days; the 64-bit debate is over, Intel has already committed to bringing an on-die memory controller to market with Nehalem and both companies agree that to address the ultra low power market, you need a new architecture.
The rule of thumb is that a single microarchitecture can cover about an order of magnitude of thermal targets, anything higher or lower and you need to look at a different architecture for maximum performance-per-watt efficiency.
AMD divides the market into two spaces: devices that have a TDP of 10 - 100W and devices that are in the 1 - 10W range. AMD has two new CPU cores that it is announcing today: Bulldozer and Bobcat, both due in 2009. Bulldozer addresses the 10 - 100W segment (much like the current K8 and Core based processors do), while Bobcat is designed for the 1 - 10W portion of the market.
BulldozerDue out in the first half of 2009, AMD's Bulldozer core is the true revolutionary successor to the K8 architecture. While Barcelona and Shanghai are both evolutionary improvements to the current core, Bulldozer is the first ground-up redesign since the K7.
Bulldozer will require a brand new socket for two reasons: it will support a new version of AMD's Direct Connect architecture (and Hyper Transport), and it will also support DDR3. Both of these changes dramatically alter the pinout of the CPU, thus making Bulldozer the next core to not be backwards compatible with current motherboards. Once again, AMD is giving us a nice roadmap for obsolescence, which its customers have always appreciated.
Details on Bulldozer are still limited, but here's a quick list of what we know about the architecture
- Not VLIW, still OoO superscalar architecture
- Deeper pipeline than Barcelona/Shanghai
- New x86 instructions targeted at HPC and "media processing"
- increased computational density
- increased flow control capability
- extend SIMD capability targeted specifically at media data types - Hyper Transport 3 will be supported
- The chip will feature 4 HT3 links
- DDR3 support - G3MX Memory Technology
- PCIe 2.0 - IOMMU (Hardware Accelerated I/O Virtualization)
A deeper pipeline than present-day architectures means we are looking at higher clock speeds, and AMD was quick to point out that there is no dramatic change in the approach to microprocessor design with Bulldozer - it's still the same type of out of order, superscalar architecture as its predecessors and not an Itanium-like design.
Extending the x86 instruction set once more only makes sense as the usage model for general purpose microprocessors becomes more demanding. AMD wouldn't be any more specific about the types of instructions we are likely to see in Bulldozer other than they would be HPC and media processing focused.
Bulldozer's connectivity will be improved, supporting up to four HT3 links per processor (up from 3 HT links in present day CPUs). With four HT3 links you can expect to see some pretty robust multi-socket configurations built around Bulldozer cores in the server/HPC markets.
Why is PCI Express 2.0 listed as a feature of the Bulldozer core? Well, some implementations of the core (think Fusion) will actually have on-die PCI Express 2.0 controllers. These CPUs will be particularly interesting for small form factor devices, because the only additional chip you will need is a South Bridge.