Intel's Memory and Storage Day event today in South Korea was mostly focused on enterprise and datacenter products, but they did announce an upcoming consumer SSD: The Intel SSD 665p. This is the successor to the Intel 660p, the first and most successful consumer SSD to use four bit per cell (QLC) NAND flash memory. The 665p isn't a major update: it keeps the same Silicon Motion SM2263 4-channel controller but updates the NAND to Intel's second-generation 96-layer 3D QLC NAND. This newer QLC keeps the same 1024Gb per-die capacity while shrinking overall die size, so we don't expect any change to the range of drive capacities offered nor any major performance changes—but it may lower prices a bit.

Intel showed off the 665p with a live demo pitting the 1TB 660p against a 1TB 665p prototype with pre-production firmware, each installed in otherwise identical ASUS notebooks. Intel used a beta version of CrystalDiskMark 7 to illustrate the 665p's performance: 40-50% improvement to sequential transfer speeds and about 30% faster random access speeds.

Left: 665p 1TB pre-production Right: 660p 1TB
(Photos by Nathan Kirsch of Legit Reviews)

Caveats: given the short test duration and relatively empty state of the drives, these numbers are measurements only of the SLC cache performance. It's not clear how much the worst-case write speeds to QLC have changed, and that's where the 660p falls far behind TLC based SSDs. The sequential IO numbers Intel showed for the 660p are also well below what we've measured with the 660p on our own testbed using CDM 7, so the sequential IO improvement might be more along the lines of 20% rather than 40-50%. Our testing of the Intel 660p also showed that it can reach similar speeds of 1.7-1.8GB/s in sequential transfers with a high enough queue depth, so the 665p's improvement here may amount to extending that performance down to queue depth 1. Either way, it looks like the 665p will be another drive that offers good enough performance for most use cases, but doesn't really need all four PCIe lanes.

Nathan Kirsch over at Legit Reviews has shared his close-up photos of the 665p alongside the 660p, so we know that the PCB layout is essentially unchanged: a single-sided M.2 2280 drive that only needs to populate all four NAND package locations for the 2TB model.

Intel hasn't shared the planned launch date for the 665p, but it should be no more than a few months away. Pricing should be comparable to the 660p, making it one of the cheapest consumer NVMe drives on the market.

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  • Alistair - Thursday, September 26, 2019 - link

    Wow, 70 MB/s random read? If true that is pretty impressive. That's faster than those PCIe 4.0 drives. I'll definitely pick one up and test it. Reply
  • Billy Tallis - Thursday, September 26, 2019 - link

    The only PCIe 4.0 consumer drives out so far use Phison controllers, and their current architecture tends to have sub-par QD1 performance because of how they handle offloading work from the relatively limited number of CPU cores to the fixed-function coprocessors on the controller. By contrast, Silicon Motion has been doing very well lately with their QD1 performance, especially of the SLC cache. Reply
  • Alistair - Thursday, September 26, 2019 - link

    It's not using the cache for read speeds. Point is it will be a QLC drive with faster read speeds than the TLC PCIe 4.0 drives that we have now, that's all, and most likely for half price. Reply
  • npz - Thursday, September 26, 2019 - link

    That doesn't make sense. If it doesn't use the SLC portion for reading then that means it has to wait for the newly added data to be first written to QLC, which would kill the performance of i.e. wrtie-then-read. The SLC cache is a part of the QLC NAND and not just a fixed write buffer Reply
  • Alistair - Thursday, September 26, 2019 - link

    Hm, maybe I don't know. My impression was that the SLC cache wasn't used for reading. I have two drives, and if I copy to the Intel 660p, it slows down after the cache is full. It doesn't slow down copying the other way from the Intel to the MLC drive, which would imply to me that it doesn't use the cache for reading... Reply
  • leexgx - Friday, September 27, 2019 - link

    SLC cache is for write buffering only (once it has filled up writes become considerably slower as it writes directly to QLC,when drive is idle it emptysto QLC)
    reads has nothing to do with SLC cache (unless its currently emptying to QLC when a read is on going)
    Reply
  • sorten - Thursday, September 26, 2019 - link

    "Caveats: given the short test duration and relatively empty state of the drives, these numbers are measurements only of the SLC cache performance" Reply
  • Alistair - Thursday, September 26, 2019 - link

    that is a blanket statement for all the tests conducted, that doesn't mean to imply that the read portion is directly affected Reply
  • TheUnhandledException - Monday, September 30, 2019 - link

    Half price? Keep dreaming. TLC is 3 bits per cell. QLC is 4 bits per cell. From a flash perspective alone you are only reducing the flash cost by 33%. Flash is only about half the total system cost (controller, SLC cache, DRAM, manufacturing, testing, shipping, retail, etc). So maybe 20% lower cost at retail. Reply
  • brruno - Tuesday, October 01, 2019 - link

    do you know that is a bit ?
    - 3 bits means you can write 8 values in a cell ( 2^3)
    - 4 bits you can write 16 values in a cell ( 2^4)
    It means that you need half the flash to achive the same storage .

    But the rest you said its true, Flash its only a part of the cost.
    Reply

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