A little under 6 months ago AMD introduced their first 300mm 90nm manufacturing facility, called Fab 36.  The name of course comes from its existence 36 years after the founding of AMD, with the plant itself being located next to Fab 30 in Dresden, Germany. 

The grand opening of Fab 36 was mostly for media attention as the plant would not begin shipping revenue parts until Q1 of 2006.  That sometime is today as AMD has just announced that Fab 36 is finally shipping revenue parts.  The parts that it is shipping are 90nm Athlon 64 and Sempron CPUs, so Opterons and Athlon 64 X2s will still come out of Fab 30 next door.  AMD cites customer demand as the reason that Athlon 64 and Sempron are first out of the new fab, which honestly makes sense; there's always need for more capacity at the lower end. 


Although both Fab 30 and Fab 36 produce 90nm processors, Fab 30 uses smaller 200mm wafers while Fab 36 features an upgrade to 300mm wafers.  AMD says that yields on 300mm wafers coming out of Fab 36 are comparable to 200mm yields being produced at Fab 30. 

A 300mm 90nm wafer from Fab 36 

In terms of capacity, by 2008 AMD plans to be able to crank out 20,000 (300mm) wafers per month out of Fab 36 which would double its microprocessor production capacity to approximately 100M CPUs per year (thanks to larger wafers and smaller transistors).  For comparison, Fab 30 currently produces 30,000 (200mm) wafers per month. Unfortunately AMD was unable to provide us with any sort of guidance as to how quickly Fab 36 will ramp up to its 20K per month target. AMD's partnership with Chartered Semiconductor Manufacturing Ltd. out of Singapore will guarantee additional 90nm production capacity beginning in the second half of this year.  By the end of this year, AMD's capacity will have increased tremendously over the single fab they had producing 90nm parts previously. 

As we mentioned in our initial coverage of Fab 36's grand opening, all parts shipping out of the plant will be 90nm, with AMD converting to 65nm starting in the second half of this year.  Fab 36 will be "substantially converted" to 65nm manufacturing by the middle of 2007.  Once again, AMD wasn't able to provide us with any sort of concrete details about the ramp to 65nm. It could very well be that AMD will be shipping lots of revenue generating 65nm parts by the end of this year, or they could be shipping very little. If the latter is true, then AMD's real transition to 65nm won't occur until far into 2007. When it does happen however, the move to 65nm will bring about smaller die sizes, faster switching transistors and lower power consumption for AMD, just as it has for Intel.  AMD's 65nm process will incorporate their third generation of SOI technology to further reduce power consumption.  AMD is promising a 40% increase in transistor performance with the move to 65nm thanks to the smaller process and the third generation SOI technology.

Fab 36 in Action

45nm and Socket-AM2


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  • Viditor - Thursday, April 6, 2006 - link


    Funny you choose the worst NetBurst Dual Core as your example

    Because it's their only dual core x86 server chip...so it's pretty much the only example possible.

    Paxville has access to a much older platform however, so I don't really take results to be of much use

    You can extrapolate results by comparing Paxville to Nocona (since it's just a Nocona MCM...)

    when AMD gets to 65nm, they won't beat Intel in the die size department, an optical shrink of Windsor to 65nm Brisbane, would be from 220mm2 to 132mm2. It would also depend if it's a straight shrink or if AMD adds more features and what not to their cores

    I'm confused here. I'm sure you're not saying that as both are at 65nm, Conroe will be smaller than Brisbane...that would be silly as it has double the cache. Also, if you look at current die pictures of AM2, you'll notice that the same amount of cache is significantly smaller on Rev F than it was on Rev E (i.e. AMD has drastically improved their cache density).
    IIRC, this began with you repeating some of the Intel marketing stuff about MCMs being a much more economical way to produce chips, but the fact that Conroe wasn't using it was irrelevant (i.e. it wouldn't reduce their yields) because they are smaller...

    As to AMD's yields, they have stated many times over the last 3 months that 65nm will START at the same yields that current 90nm chips enjoy (mature yields). They have even shown how this is possible with APM and given an example with their 90nm process which was close to mature yields at it's launch.

    How do you disagree again, as NetBurst doesn't have shared cache, not at the consumer level at least, so they communicate through the FSB anyway. Since the NetBurst design communicates through the FSB, the DUal Die implementation is fine...

    I disagreed with your comment about the ODMC making a difference. I don't believe there is anything inherent in the NetBurst uA that precludes it from being a true dual core (either with a shared cache or DCA)...except of course that Intel didn't plan for it. Therefore (as you say), for NetBurst chips, MCMs were the only possible way to go. IMHO, the "yield advantage" is just Intel's way of "making lemonade"...
    I still see no reason why NGMA cores will fare any better with MCM than their NetBurst brethren did.

    This brings up a last point...will AMD go MCM as well? Most of us are assuming that they will continue with DCA for their cores, but all of the Hammers have been DC designs since the very beginning. I have no idea as to whether or not the AMD Quad Cores are true quads or MCMs. If anybody knows for a fact one way or another, please post!
  • coldpower27 - Thursday, April 6, 2006 - link

    I am not gonna have to take extrapolations using NetBurst architecture as a template as pretty much useless. The FSB bandwidth avaialble to Core Architecture will be significantly enhanced in comparison to what Paxville or Nocona has access to.

    The NetBurst Architecture is too bandwidth dependent to serve as a good indicator of how Core Architecture will react.

    I am saying Intel will have an advantage with Allendale vs Brisbane 2 processors with equal amount of total LV2 cache. Not in relation to Conroe. With Conroe it is unknown as it would be a fairly mature product by that timeframe, so it's hard to compare yield between AMD and Intel.

    The definition of mature yields has been vague to me at best, perhaps it means that entering into the 65nm process they will have equal to greater output then can be had on the mature 90nm process going out... Not an issue really for desktops till H1 2007 however. Indications look like AMD will try to concentrate on the server and mobile segements with their 65nm production.

    "True Dual Core" your actually spouting that AMD propaganda??? Dual Core says there only has to be 2 cores, their isn't anything in the definition that limits it to a monolitic die vs MCM module. Presler is no less "true" then Toledo, maybe you should stick to the monolithic vs MCM argument instead of using vague terminology as "true".
    It's common knowledge that a smaller die is easier to yield then a larger one on a given process, it simply a matter of more surface area for a defect to occur. Your opinion of the making lemonade part is jsut that your opinion which I don't agree with, NetBurst Dual Core designs wasn't amazing as it wasn't design to be a Dual Core that is true from what Intel has spoken on the subject, but the solution cranked out was an acceptable one for something that had no intention of moving to Dual Core.

    There isn't a point in making a monolithic design for NetBurst now as Intel is moving to a more integrated design like AMD did, where the two cores work more closely like in Conroe with Shared LV2. Why spend resources to improve the old NetBurst Architecture, when you have sometihng much better in the works.

    Well a surprise for you is that Tulsa the Xeon MP core will based based on Netburst MicroArchitecture and will have access to 16MB of Shared LV3 cache.

    Can AMD go MCM at all? I mean with how closely their cores are working together with their ODMC shared between the two cores.

    It won't matter in the end though, we'll get monolithic quad core designs out of Intel on the 45nm node when it's more economical to do so and hence having the ability for each core to work more closely with the other 3. The 65nm versions are just first interations to wet the peoples appetite for better quad cores as we go down the road.

    I am not saying a MCM design is great for performance either, but it's important to see how adversely Core Architecture will be affected, since even going through a FSB that is 1.33GHZ is alot better then the 800MHZ FSB that Paxville's platform was stuck with. I am all for a monolithic die package Quad Core when economically feasable, but a MCM design in the meantime is an adequate solution to introduce Quad Core.

  • Viditor - Thursday, April 6, 2006 - link


    I am not gonna have to take extrapolations using NetBurst architecture as a template as pretty much useless

    Not for determining the penalty that MCM incurs it isn't...though it would be for determining the exact performance of Kentsfield (we haven't actually benched them yet).

    The FSB bandwidth avaialble to Core Architecture will be significantly enhanced in comparison to what Paxville or Nocona has access to

    It's true that Intel will be increassing the FSB from 800MHz to 1333MHz (an increase of 40%), but for quad core you will also be increasing the number of cores by 100%...

    Dual Core says there only has to be 2 cores

    Sorry, but where does it "say" that? Both "Dual" and "Twin" mean 2...however Dual implies identical and connected while twin implies not connected but identical. Doesn't it make more sense and seem clearer to call an MCM a "twin" core for clarification?

    the solution cranked out was an acceptable one for something that had no intention of moving to Dual Core

    We shall have to agree to disagree then...IMHO, the twin core solution did allow Intel to save a bit of face, but as their sales and reviews of twin core CPUs was so dismal, I would hardly call it acceptable.

    Can AMD go MCM at all? I mean with how closely their cores are working together with their ODMC shared between the two cores

    That's assuming a single ODMC...just as Intel is going to a 2 FSB model, AMD could use a dual ODMC model on quad core. Then, all they would need is a cHT link between the cores (just as like it is between cores on current Opteron MP chips). This would solve a problem and create one.
    1. Latency for cache coherency would increase, but only slightly
    2. memory bandwidth would double per CPU
    A main advantage over Intel though is that it would be a cHT link rather than arbitration through the FSB...just hypothesizing here.
  • MrKaz - Wednesday, April 5, 2006 - link

    Yes but i still tell you the same:

    For each 1000 processor cores build intel sells 500 processors... half of production, is also a huge hit. I'm not saying AMD implementation is better...

    Celeron is only 256kb cache not 512kb.
  • coldpower27 - Wednesday, April 5, 2006 - link

    I was talking the Cedar mill revision, that will be released soon, right now they are still based on Prescott so 256KB yes, the Cedar Mill version will be 512kb.

    Intel sells 500 Dual Cores, or it could be 250 Dual Cores and 500 Single Cores, it depends on market needs.
  • her34 - Wednesday, April 5, 2006 - link

    what's intel's total production capacity? Reply
  • logeater - Tuesday, April 4, 2006 - link

    Poor AMD. All this spin doctoring has left them to dizzy to actually know what they are doing. The AM2 will struggle to get anywhere near Conroe if you are smart enough read between the lines.

    Time to take out my stocks in AMD and pump them into Intel me thinks. ;)

  • Viditor - Wednesday, April 5, 2006 - link


    Time to take out my stocks in AMD and pump them into Intel me thinks

    Cool...that'll be me on the other end of that transaction! :)
  • MrKaz - Wednesday, April 5, 2006 - link

    Well Intel in the last 3 years has been lagging behind Intel. What’s the problem if Intel leaves AMD behind during some months or a year or two?

    That doesn’t mean Intel is superior. Right now still seems inferior to me...
  • MrKaz - Wednesday, April 5, 2006 - link

    Well Intel in the last 3 years has been lagging behind AMD. Reply

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