What Products Use Intel 10nm? SuperFin and 10++ Demystified
by Dr. Ian Cutress on September 25, 2020 9:00 AM ESTThe AnandTech Decoder Ring for Intel 10nm
The reason why I’m writing about this topic is because it is all a bit of a mess. Intel is a company so large, with many different business units each with its own engineers and internal marketing personnel/product managers, that a single change made by the HQ team takes time to filter down to the other PR teams, but also filter back through the engineers, some of which make press-facing appearances. That’s before any discussions as to whether the change is seen as positive or negative by those affected.
I reached out to Intel to get their official decoder ring for the 10++ to new SuperFin naming. The official response I received was in itself confusing, and the marketing person I speak to wasn’t decoding from the first 2018 naming change, but from the original pre-2017 naming scheme. Between my contacts and I we spoke over the phone so I could hear what they wanted to tell me and so I could tell them what I felt were the reasons for the changes. Some of the explanations I made (such as Intel not wanting to acknowledge Ice Lake 10nm is different to Cannon Lake 10nm, or that Ice Lake 10nm is called that way to hide the fact that Cannon Lake 10nm didn’t work) were understandably left with a no comment.
However, I now have an official decoder ring for you, to act as a reference for both users and Intel’s own engineers alike.
| AnandTech's Decoder Ring for Intel's 10nm | ||||
| Product | 2020+ | First Update |
Original |
|
| Cannon Lake | - | - | 10nm | |
| Ice Lake Ice Lake-SP Lakefield (compute) Snow Ridge Elkhart Lake |
10nm | 10nm | 10+ | |
| Tiger Lake SG1 DG1 |
10nm Superfin |
10+ | 10++ | |
| Alder Lake First Xe-HP GPU Sapphire Rapids |
10nm Enhanced SuperFin |
10++ | 10+++ | |
For clarity, 10nm Superfin is often abbreviated to 10SF, and 10nm Enhanced Superfin to 10ESF.
Moving forward, Intel’s communications team is committed to explaining everything in terms of 10nm, 10SF, and 10ESF. I have been told that the process of moving all internal documents away from the pre-2017 naming to the 2020 naming is already underway.
We reached out for Intel for a comment for this article:
It is widely acknowledged within the industry that there is inconsistency and confusion in [our] nanometer nomenclature. Going forward, we will refer the next generation 10nm products as 10nm SuperFin technology-based products.
My take is that whoever had the bright idea to knock Ice Lake down from 10+ to 10 (and then Tiger from 10++ to 10+ etc.), in order to protect the company from addressing issues with the Cannon Lake product, drastically failed at predicting the fallout that this name change would bring. Sometimes a company should accept they didn't score as well as they did, admit the hit, and move on, rather than try and cover it up. So much more time and effort has been lost in terms of communications between the press and Intel, or the press and engineers, or even between the engineers and Intel's own communications team. Even the basic understanding of dealing with that change has been difficult, to the detriment of the press trying to report on Intel’s technology, and likely even on the financial side as investors try to understand what’s going on.
But, truth be told, I’m glad that Intel moved away from the ++++ nomenclature. It allows the company to now easily name future manufacturing node technologies that aren’t just for pure logic performance, which may be vital if Intel ever wants to become a foundry player again.
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lilo777 - Friday, September 25, 2020 - link
I totally agree. People obsessed with process names should check this article - https://hexus.net/tech/news/cpu/145645-intel-14nm-...It shows that transistor density of Intel 14nm+++ is close to that of AMD/TSMC 7nm.
Spunjji - Friday, September 25, 2020 - link
It really isn't when you compare the whole chip - they appear to have compared some of the worst structures for scaling in that article.Nobody's really obsessed with names - they just serve a useful purpose for discussing differences.
lilo777 - Friday, September 25, 2020 - link
They are not. After advent of finfet (and maybe even before it) process names do not carry any useful information about the merits of the process. It's just a name of the menu item in foundry's catalog. If they wanted to, Intel could name their next process 1nm. They won't. Nobody cares.Spunjji - Monday, September 28, 2020 - link
Process names stopped relating to most structure sizes way before FinFet, and I'm well aware that the name itself - on its own - doesn't convey useful information about the process. What they do convey is which process came after which for a given foundry, they imply significant difference such as a decrease in average feature size, and sometimes they convey a general idea of which industry generation the process belongs to. what they don't tell you is whose foundry produces smaller and/or more performant transistors, but as I said in the first place, they're useful as a simple reference point for discussion; you can't easily discuss something that doesn't have a name.Intel won't name their next generation 1nm because it wouldn't be the next logical step after their current generation. You're literally proving yourself wrong by pointing out that they won't do that.
You also totally skipped past copping to the falsehood that 14nm+++ is "close to" TSMC 7nm. 14nm++ is around 37.22 MTr/mm² (Source: https://en.wikichip.org/wiki/mtr-mm%C2%B2 ) while Renoir on 7nm measures in at about 63 MTr/mm².
FullmetalTitan - Saturday, September 26, 2020 - link
That TEM cut looks an awful lot like SRAM block, which has notoriously poor scaling with design node. SRAM cells from 28nm generations are not double the size of 14nm SRAM cells, more like 20% larger.However as you point out in your next comment, node naming stopped being a useful metric, somewhere between 65nm and 45nm. The industry stuck with it based on IEEE roadmap of full-node step naming, but it doesn't remotely align with the reality. The old standard was full width half pitch, since the center to center distance between gates was approximately aligned with the channel width. Intel led the industry departure from that standard, instead measuring the effective gate length. In later generations of planar nodes (45nm and smaller) gates were packed densely enough that FWHP was not accurately representing gate width anymore, it was SMALLER than the gate dimension. With FINFETs that actually went a bit far in the other direction since the control surface width of a fin is not the same as a planar device, since the gate wraps over the fin and the surface area is the important factor in design and operation. For the 14/16nm generation of devices, the minimum feature size of interest was actually 6-7nm for Intel, TSMC, and Samsung nodes.
Spunjji - Monday, September 28, 2020 - link
Yup, you nailed it on that one. False conclusion (similar density) drawn from incomplete information (only one type of transistor measured).RSAUser - Saturday, September 26, 2020 - link
These are all from "IC Knowledge LCC" as posted by electronics weekly.Transistor density (MTx/mm2)
Intel 10nm: 106
Samsung 5LPE: 133.56
TSMC 5FF: 185.46
Then from other places, this is Wikipedia, but following links to check that they're right:
TSMC N7FF (First generation 7nm): 96.5
So TSMC's first 7nm generation is nearly as dense as Intel's first 10nm, interesting. Meanwhile TSMC's N7FF+ is 114, Apple's A13 chip is built on this.
Their 5nm node is supposedly 186, it's used for Apple's A14 chip.
Spunjji - Monday, September 28, 2020 - link
That number for Intel 10nm isn't accurate - it was their original target and it hasn't been reached in practice. It looks like they had to relax a lot of their design rules to make the process yield well.Anandtech's quoted number for density with Lakefield is 49.4 MTr/mm², while apparently Tiger Lake is closer to 40 MTr/mm².
Bagheera - Tuesday, March 9, 2021 - link
you should check this article:https://semiwiki.com/semiconductor-services/ic-kno...
it's by someone who actually know we what they are taking about.
Ian Cutress - Friday, September 25, 2020 - link
Billions of dollars go into process steps. Talking about next gen processors isn't all about performance - it's the industry of the hardware that goes into building machines to enable those processes. Hundreds of thousands of jobs, supply chains, the works. So yes, we do care about process node technology. A whole friggin lot.I once heard from an Intel exec that told a bunch of press who started asking about 10nm that 'process node doesn't matter'. I came down on him like a ton of bricks. I haven't seen him speak to the press since. I hope it's not you.