Sapphire Rapids

As with any processor vendor, having a detailed list of what the processor does and how to optimize for it is important. Helping programmers also plan for what’s coming is also vital. To that end, we often get glimpses of what is coming in future products by keeping track of these updates. Not only does it give detail on the new instructions, but it often verifies code names for products that haven’t ‘officially’ been recognized. Intel’s latest update to its ISA Extensions Reference manual does just this, confirming Alder Lake as a future product, and identifies what new instructions are coming in future platforms. Perhaps the biggest news of this is actually the continuation of BFLOAT16 support, originally supposed to be Cooper Lake only...

Cadence DDR5 Update: Launching at 4800 MT/s, Over 12 DDR5 SoCs in Development

JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which...

20 by Anton Shilov on 3/27/2020

Analyzing Intel’s Discrete Xe-HPC Graphics Disclosure: Ponte Vecchio, Rambo Cache, and Gelato

It has been a couple of weeks since Intel formally provided some high-level detail on its new discrete graphics strategy. The reason for the announcements and disclosures centered around...

47 by Dr. Ian Cutress on 12/24/2019

Intel’s 2021 Exascale Vision in Aurora: Two Sapphire Rapids CPUs with Six Ponte Vecchio GPUs

For the last few of years, when discussing high performance computing, it has been tough to avoid hearing the word ‘exascale’. Even last month, on 10/18, HPC twitter was...

43 by Dr. Ian Cutress on 11/17/2019

Intel Xeon Update: Ice Lake and Cooper Lake Sampling, Faster Future Updates

Emerging workloads will require considerably higher performance, and in order to solve upcoming challenges Intel has adjusted its product roadmaps quite significantly. One of the key things that Intel...

29 by Anton Shilov on 5/9/2019

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