Security Updates, Improved Instruction Performance and AVX-512 Updates

With every new microarchitecture update, there are goals on several fronts: add new instructions, decrease the latency of current instructions, increase the throughput of current instructions, and remove bugs. The big headline addition for Sunny Cove and Ice Lake is AVX-512, which hasn’t yet appeared on a mainstream widely distributed consumer processor – technically we saw it in Cannon Lake, but that was a limited run CPU. Nonetheless, a lot of what went into Cannon Lake also shows up in the Sunny Cove design. To complicate matters, AVX-512 comes in plenty of different flavors. But on top of that, Intel also made a significant number of improvements to a number of instructions throughout the design.

Big thanks to InstLatX64 for his help in analyzing the benchmark results.

Security

On security, almost all the documented hardware security fixes are in place with Sunny Cove. Through the CPUID results, we can determine that SSBD is enabled, as is IA32_ARCH_CAPABILITIES, L1D_FLUSH, STIBP, IBPB/IBRS and MD_CLEAR.

This aligns with Intel’s list of Sunny Cove security improvements:

Sunny Cove Security
AnandTech Description Name Solution
BCB Bound Check Bypass Spectre V1 Software
BTI Branch Target Injection Spectre V2 Hardware+OS
RDCL Rogue Data Cache Load V3 Hardware
RSSR Rogue System Register Read V3a Hardware
SSB Speculative Store Bypass V4 Hardware+OS
L1TF Level 1 Terminal Fault Foreshadow Hardware
MFBDS uArch Fill Buffer Data Sampling RIDL Hardware
MSBDS uArch Store Buffer Data Sampling Fallout Hardware
MLPDS uArch Load Port Data Sampling - Hardware
MDSUM uArch Data Sampling Uncachable Memory - Hardware

Aside from Spectre V1, which has no suitable hardware solution, almost all of the rest have been solved through hardware/firmware (Intel won’t distinguish which, but to a certain extent it doesn’t matter for new hardware). This is a step in the right direction, but of course it may have a knock-on effect, plus for anything that gets performance improvements being moved from firmware to hardware will be rolled into any advertised IPC increase.

Also on the security side is SGX, or Intel’s Software Guard Instructions. Sunny Cove now becomes Intel’s first public processor to enable both AVX-512 and SGX in the same design. Technically the first chip with both SGX and AVX-512 should have been Skylake-X, however that feature was ultimately disabled due to failing some test validation cases. But it now comes together for Sunny Cove in Ice Lake-U, which is also a consumer processor.

Instruction Improvements and AVX-512

As mentioned, Sunny Cove pulls a number of key improvements from the Cannon Lake design, despite the Cannon Lake chip having the same cache configuration as Skylake. One of the key points here is the 64-bit division throughput, which goes from a 97-cycle latency to an 18-cycle latency, blowing past AMD’s 45-cycle latency. As an ex-researcher with no idea about instruction latency or compiler options, working on high-precision math code, this speedup would have been critical.

  • IDIV -> 97-cycle to 18-cycle

For the general purpose registers, we see a lot of changes, and most of them quite sizable.

Sunny Cove GPR Changes
AnandTech Instruction Skylake Sunny Cove
Complex LEA Complex Load Effective Address 3 cycle latency
1 per cycle
1 cycle latency
2 per cycle
SHL/SHR Shift Left/Right 2 cycle latency
0.5 per cycle
1 cycle latency
1 per cycle
ROL/ROR Rotate Left/Right 2 cycle latency
0.5 per cycle
1 cycle latency
1 per cycle
SHLD/SHRD Double Precision Shift Left/Right 4 cycle latency
0.5 per cycle
4 cycle latency
1 per cycle
4*MOV Four repated string MOVS Limited instructions 104 bits/clock
All MOVS* Instructions

In the past we’ve seen x87 instructions being regressed, made slower, as they become obsolete. For whatever reason, Sunny Cove decreases the FMUL latency from 5 cycles to 4 cycles.

The SIMD units also go through some changes:

Sunny Cove SIMD
AnandTech Instruction Skylake Sunny Cove
SIMD Packing SIMD Packing now slower 1 cycle latency
1 per cycle
3 cycle latency
1 per cycle
AES* AES Crypto Instructions
(for 128-bit / 256-bit)
4 cycle latency
2 per cycle
3 cycle latency
2 per cycle
CLMUL Carry-Less Multiplication 7 cycle latency
1 per cycle
6 cycle latency
1 per cycle
PHADD/PHSUB Packed Horizontal Add/Subtract
and Saturate
3 cycle latency
0.5 per cycle
2 cycle latency
1 per cycle
VPMOV* xmm Vector Packed Move 2 cycle latency
0.5 per cycle
2 cycle latency
1 per cycle
VPMOV* ymm Vector Packed Move 4 cycle latency
0.5 per cycle
2 cycle latency
1 per cycle
VPMOVZX/SX* xmm Vector Packed Move 1 cycle latency
1 per cycle
1 cycle latency
2 per cycle
POPCNT Microcode 50% faster than SW (under L1-D size)
REP STOS* Repeated Store String 62 bits/cycle 54 bits/cycle
VPCONFLICT Still Microcode Only

We’ve already gone through all of the new AVX-512 instructions in our Sunny Cove microarchitecture disclosure. These include the following families:

  • AVX-512_VNNI (Vector Neural Network Instructions)
  • AVX-512_VBMI (Vector Byte Manipulation Instructions)
  • AVX-512_VBMI2 (second level VBMI)
  • AVX-512_ BITALG (bit algorithms)
  • AVX-512_IFMA (Integer Fused Multiply Add)
  • AVX-512_VAES (Vector AES)
  • AVX-512_VPCLMULQDQ (Carry-Less Multiplacation of Long Quad Words)
  • AVX-512+GFNI (Galois Field New Instructions)
  • SHA (not AVX-512, but still new)
  • GNA (Gaussian Neural Accelerator)

(Intel also has the GMM (Gaussian Mixture Model) inside the core since Skylake, but I’ve yet to see any information on this outside a single line in the coding manual.)

For all these new AVX-512 instructions, it’s worth noting that they can be run in 128-bit, 256-bit, or 512-bit mode, depending on the data types passed to it. Each of these can have corresponding latencies and throughputs, which often get worse when going for the 512-bit mode, but overall assuming you can fill the register with a 512-bit data type, then the overall raw processing will be faster, even with the frequency differential. This doesn’t take into account any additional overhead for entering the 512-bit power state, it should be noted.

Most of these new instructions are relatively fast, with most of them only 1-3 cycles of latency. We observed the following:

Sunny Cove Vector Instructions
AnandTech Instruction XMM YMM ZMM
VNNI Latency Vector Neural Network Instructions 5-cycle 5-cycle 5-cycle
Throughput 2/cycle 2/cycle 1/cycle
VPOPCNT* Latency Return the number of bits set to 1 3-cycle 3-cycle 3-cycle
Throughput 1/cycle 1/cycle 1/cycle
VPCOMPRESS* Latency Store Packed Data 3-cycle 3-cycle 3-cycle
Throughput 0.5/cycle 0.5/cycle 0.5/cycle
VPEXPAND* Latency Load Packed Data 5-cycle 5-cycle 5-cycle
Throughput 0.5/cycle 0.5/cycle 0.5/cycle
VPSHLD* Latency Vector Shift 1-cycle 1-cycle 1-cycle
Throughput 2/cycle 2/cycle 1/cycle
VAES* Latency Vector AES Instructions 3-cycle 3-cycle 3-cycle
Throughput 2/cycle 2/cycle 1/cycle
VPCLMUL Latency Vector Carry-Less Multiply 6-cycle 8-cycle 8-cycle
Throughput 1/cycle 0.5/cycle 0.5/cycle
GFNI Latency Galois Field New Instructions 3-cycle 3-cycle 3-cycle
Throughput 2/cycle 2/cycle 1/cycle

For all of the common AVX2 instructions, xmm/ymm latencies and throughputs are identical to Skylake, however zmm is often a few cycles slower for DIV/SQRT variants.

Other Noticeable Observations

From our testing, we were also able to prove some of the other parts of the core, such as the added store ports and shuffle units.

Our data shows that the second store port is not identical to the first, which explains the imbalance when it comes to writes: rather than supporting 2x64-bit with loads, it only supports either 1x64-bit write, or 1x32-bit write, or 2x16-bit writes. This means we mainly see speed ups with GPR/XMM data, and the result is only a small improvement for 512-bit SCATTER instructions. Otherwise, it seems not to work with any 256-bit or 512-bit operand (you can however use it with 64-bit AVX-512 mask registers). This is going to cause a slight headache for anyone currently limited by SCATTER stores.

The new shuffle unit is only 256-bit wide. It will handle a number of integer instructions (UNPCK, PSLLDQ, SHUF*, MOVSHDUP, but not PALIGNR or PACK), but only a couple of floating point instructions (SHUFPD, SHUFPS).

Cache and TLB Updates SPEC2017 and SPEC2006 Results (15W)
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  • Ratman6161 - Wednesday, August 7, 2019 - link

    "Did we really learn something new from this piece? Not really would be my answer."
    Actually I learned something. To me this showed that once Ice Lake systems hit the market, it will be time for me to start looking for a deal on A Whiskey Lake system. We see potential performance increases in some things but not others and the things more interesting to me personally fall into the tests where there isn't much difference.

    Besides, everyone understands this is a pre-release system and much more data will be needed to really make a decision...at least I thought everyone understands. My personal experience with laptops in general has been that how good the cooling performance is is probably the most important factor in real world performance as most of them will thermal throttle long before you get any kind of sustained performance out of them anyway.
    Reply
  • casperes1996 - Thursday, August 1, 2019 - link

    Don't let comments like this get to you, Ian.

    It was an excellent article, considering the limited time you had with the platform. There will always be people calling fanboyism or the like no matter which company is in focus. You balanced it all as well as you could with the time you had the device for, and it was a great read.
    If anything I'd actually say it sometimes came off as being a bit anti-Intel; Not in terms of their products, but the whole thing with them trying to involve themselves more in how you test their stuff, perhaps to their advantage. Sometimes sounded a bit "Just let me do my job and I'll let you do yours". But I thought that was kinda good ;)
    Reply
  • eva02langley - Friday, August 2, 2019 - link

    Well, the thing is more about the free advertisement. You are not the only one who went there. Toms did and their testing are downright different from yours. I believe your numbers way more than theirs, however there is a cost of being part of scheme like this. Reply
  • CityBlue - Saturday, August 3, 2019 - link

    > We do our own validation of the platform to remove as much Intel involvement as possible.

    You say that, but it's difficult to believe Anandtech can be trusted when you botched the Ryzen 3 benchmark reviews so so badly and have subsequently been in denial ever since (looking at you, Ryan on reddit).

    You personally have suggested that security isn't important so any performance impact resulting from security mitigations doesn't sound like something you would personally care about, thus playing right into the hands of a firm like Intel.

    So, can you trusted? That would be a big fat "no" from me, I'm afraid.
    Reply
  • Jorgp2 - Thursday, August 1, 2019 - link

    Lol, this is exactly what qualcomm does.

    Its just a preview, they will do better testing at release.
    Reply
  • brakdoo - Thursday, August 1, 2019 - link

    Yeah the Qualcomm pieces were problematic too because they could have just released a few benchmarks (and they did) to give us a rough understanding of the performance.

    The real power consumption and performance (especially therm. throttled) came later in real world tests.

    It was not until Andrei compared the 855 to the Kirin 980 when we saw the Kirin to be slightly faster and more efficient in pure CPU tests.

    At least Qualcomm made real statements about release dates and those chips being really high volume. We still don't know whether or not Ice Lake will be in just a few laptops.
    Reply
  • Andrei Frumusanu - Thursday, August 1, 2019 - link

    The 855 preview contained almost our whole test suite, with just the thermal GPU tests missing due to lack of time.

    > It was not until Andrei compared the 855 to the Kirin 980 when we saw the Kirin to be slightly faster and more efficient in pure CPU tests.

    This was included in the preview, and not later:

    https://www.anandtech.com/show/13786/snapdragon-85...

    The S10 review essentially had no changes on those numbers.
    Reply
  • Valantar - Saturday, August 3, 2019 - link

    brakdoo: your stance here is nonsense. You're arguing that it's _more_ problematic to accept special access to do your own independent testing than it is to simply accept a company's marketing statements in good faith? That makes _zero_ sense, and is certainly not how journalism is supposed to work. Articles like this are very valuable as they give interested readers information that can be trusted to a certain degree (even if the test platform isn't what they're going to be buying in the future), unlike marketing statements which always have some spin.

    Ian: Excellent article, and good job getting all that work done in just eight hours. Keep up the good work.
    Reply
  • FunBunny2 - Thursday, August 1, 2019 - link

    "Now 5G is just sub-6 and the only important part is massive MIMO"

    cute. I've been, ever since 5G was a twinkle in the eye of whoever, that mmWave 5G was, and always will be, vaporware. getting it to work in the real world, when engineers and scientists have known for decades how microwave (and near) propagates, is a non-starter. the telecom BS has reached ever new highs.
    Reply
  • Eletriarnation - Thursday, August 1, 2019 - link

    This seems like a good thing to me - we're getting useful information earlier, even if it is limited in scope. It's not like AMD offered the same and you turned them down. Keep up the good work! Reply

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