The Ice Lake Benchmark Preview: Inside Intel's 10nm

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• tamalero - Monday, August 5, 2019 - link

  the 3d mark VRS test graph is very confusing.

• MASSAMKULABOX - Tuesday, August 6, 2019 - link

  These chips are priced quite high esp the i3's the Dualcore is outrageous (20$ discount for half the cores and threads?).They will only sell in limited qtys at such high prices . Bring on the 14nm equiv at sane prices.
  what discrete gfx does the IGPU equate to? gt1030 vs 2200g vs 3400ge??

• Zhentar - Tuesday, August 6, 2019 - link

  The bit per cycle throughput of REP STOS is really only half of the picture - the startup latency matters a lot too! On my Skylake, I've measured a minimum latency of 29 cycles* (any REP STOS from 1 byte to 128 bytes takes 29 cycle, then it starts going up from there). Some compilers make heavy use of it even for small stores/copies (VC6, first and foremost, but also the .NET JIT for stack zeroing), so it can be pretty important to performance in some scenarios.
  
  *I am no Agner Fog... nor anywhere close to him, this measurement should be taken with a grain of salt ;-)

• ballsystemlord - Wednesday, August 7, 2019 - link

  
  @Ian
  Sunny Cove SIMD chart and others have many asterisks, why?
  
  "POPCNT Microcode 50% faster than SW (under L1-D size)"
  What does this mean? The CPU uses microcode and HW, not SW, AFAIK, much less use it to implement the POPCNT instruction.

• ballsystemlord - Thursday, August 8, 2019 - link

  Spelling and grammar errors:
  Insert: I've been commenting corrections for at least 1 year now, if you guys want me to change the format, or have any request regarding phrasing, etc., just ask. Thanks for your work!
  
  "L3 latencies look similar, however we'll dwell into that just in a bit."
  I think you ment delve:
  "L3 latencies look similar, however we'll delve into that just in a bit."
  
  "IPC increases against the mobile Skylake are 33 and 38% in the integer and fp suites, though we also have to keep in d mind these figures go beyond just the Sunny Cove architecture and also include improvements through the new LPDDR4X memory controllers."
  Missing percent sign and stray "d".
  "IPC increases against the mobile Skylake are 33% and 38% in the integer and fp suites, though we also have to keep in mind these figures go beyond just the Sunny Cove architecture and also include improvements through the new LPDDR4X memory controllers."
  
  "...which did not go down to well."
  You mean "too" not "to":
  "...which did not go down too well."
  
  "...we actually see a number of key microarchitectural improvements bubble up through in our SPEC testing."
  Excess "in":
  "...we actually see a number of key microarchitectural improvements bubble up through our SPEC testing."

• alysdexia - Thursday, November 28, 2019 - link

  I think you mean Baalsystemlord or Bàqhàlsýstemlord.
  Grammar is a barbarism of ghrammatics, another word for composition or handwriting, font, format, spacing, the looks, whereas you meant diction/lecsis or register, vocabulary, declension, placement, spelling, the meaning.
  you guys -> ye

• nils_ - Monday, August 19, 2019 - link

  I noticed on Intel Ark that Ice Lake CPUs do not have TSX instructions enabled / available. THis is interesting, since I believe TSX has also been used for some of the spectre attacks.

• ikjadoon - Thursday, September 12, 2019 - link

  On 'Gaming Results (15W and 25W)', the graph is colored incorrectly. "On" and "Off" have the same color...and the legend colors are somehow not related to the graphic?