Examining Intel's Ice Lake Processors: Taking a Bite of the Sunny Cove Microarchitecture
by Dr. Ian Cutress on July 30, 2019 9:30 AM EST- Posted in
- CPUs
- Intel
- 10nm
- Microarchitecture
- Ice Lake
- Project Athena
- Sunny Cove
- Gen11
Two Versions, Two Different Power Targets
Intel has promised that Ice Lake-U will be seen in a variety of form factors, targeting anywhere from 9W to 28W. This sort of range is not new for a U-series processor – we typically see overlap from something lower down (the Y-series, ~5W) or higher up (H-series, ~45W), however Ice Lake hasn’t currently been listed for H series power budgets - only Y and U. Having such a wide window, from 5-28W, allows Intel to be very wide with binning the chips as they come of the production line, which is a very valid tactic for promoting as much yield as possible with minimal waste.
Technically there will be two different Ice Lake BGA mobile packages – one aimed at low power (7-12W) for the Y series, and another for higher power designs (15-28W) in the U series.
At this point Intel has not stated what core configurations will be in both packages, however it is likely that the lower power 7-12W ‘Type 4’ package will be for Y-series implementations only, especially given that the overall package size is only 490mm2 (26.5x18.5) compared to 1250 mm2 (50x25), making it 39% the size of the larger high power package. It stands to reason then that the smaller package is for lower performance and low power options, despite being exactly the same silicon.
This Type-4 option also uses the ‘recessed in board’ design we first saw with Broadwell-Y, which is required based on the integrated voltage regulators that Intel now uses on its low powered designs. This makes a very interesting point about Intel’s capabilities with low powered 10nm designs: one could postulate that as the recessed model is well above the traditional Y-series power line. If the 10nm process doesn’t go low down enough in power to that sub-5W range, it could either be because of power, or there isn't enough frequency for Intel to actually sell at volume. Alternatively Intel could end up increasing the base power of the Y-series. One could draw parallels with the first generation 10nm Cannon Lake Core i3-8121U at 15W, which was initially postulated to be dual-core Y-series silicon, rather than the 15W U-series designation it ended up with (our review showed that it did indeed consume more power for the same work compared to a 14nm equivalent design, which would imply a very high static power). With this in mind, it makes me wonder what percentage of Type 3 / Type 4 package designs Intel will end up shipping into the market.
Broadwell Motherboard Design for Recessed Power Implementation
Intel is keen to promote that one of the new features of Ice Lake is its Thin Magnetic Inductor Array, which helps the FIVR achieve better power conversion efficiencies and waste less power. The main issue with a FIVR is at low power consumption states that have a lot of inefficiency – some other processor designs have a linear LDO (Low-Dropout Regulator) implementation which is better for low power designs but less efficient in high power modes.
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repoman27 - Tuesday, July 30, 2019 - link
“Each CPU has 16 PCIe 3.0 lanes for external use, although there are actually 32 in the design but 16 of these are tied up with Thunderbolt support.”This isn’t quite right. The ICL-U/Y CPU dies do not expose any PCIe lanes externally. They connect to the ICL PCH-LP via OPI and the PCH-LP exposes up to 16 PCIe 3.0 lanes in up to 6 ports via HSIO lanes (which are shared with USB 3.1, SATA 6Gbps, and GbE functions). So basically no change over the 300 Series PCH.
The integrated Thunderbolt 3 host controller may well have a 16-lane PCIe back end on-die, and I’m sure the CPU floorplan can accommodate 16 more lanes for PEG on the H and S dies, but that’s not what’s going on here.
voicequal - Friday, August 2, 2019 - link
The SoC architecture shows a direct path for the Thunderbolt3 PCIe lanes to the CPU, with only USB2 going across OPI.. Whatever PCIe lanes are available on the PCH are in addition those available via TB3.https://images.anandtech.com/doci/14514/Blueprint%...
repoman27 - Tuesday, August 6, 2019 - link
The Thunderbolt 3 controller is part of the CPU die. There are four PCIe 3.0 x4 root ports connected to the CPU fabric that feed the Thunderbolt protocol converters connected to the Thunderbolt crossbar switch (the Converged I/O Router block in that diagram). The CPU exposes up to three (for Y-Series) or four (for U-Series) Thunderbolt 3 ports. The only way you can leverage the PCIe lanes on the back-end of the integrated Thunderbolt 3 controller is via Thunderbolt.The PCH is a separate die on the same package as the CPU die. The two are connected via an OPI x8 link operating at 4 GT/s which is essentially the equivalent of a PCIe 3.0 x4 link. The PCH contains a sizable PCIe switch internally which connects to the back-ends of all of the included controllers and also provides up to 16 PCIe 3.0 lanes in up to 6 ports for connecting external devices. These 16 lanes are fed into a big mux which Intel refers to as a Flexible I/O Adapter (FIA) along with all the other high-speed signals supported by the PCH including USB 3.1, SATA 6Gbps, and GbE to create 16 HSIO lanes which are what is exposed by the SoC. So there are up to 16 PCIe lanes available from the Ice Lake SoC package, all of which are provided by the PCH die, but they come with the huge asterisk that they are exposed as HSIO lanes shared with all of the other high-speed signaling capabilities of the PCH and provisioned by a PCIe switch that effectively only has a PCIe 3.0 x4 connection to the CPU.
This is not at all what Ian seemed to be describing, but it is the reality.
And the USB 2.0 signals for the Thunderbolt 3 ports do indeed come from the PCH, but they do not cross the OPI, they're simply routed from the SoC package directly to the Thunderbolt port. The Thunderbolt 3 host controller integrated into the CPU includes a USB 3.1 xHCI/xDCI but does not include a USB 2.0 EHCI.
poohbear - Tuesday, July 30, 2019 - link
I was looking at buying Dell's XPS 15.6" (7590 model), but with Project Athena laptops a few months away, i think i'll wait. Intel parts for solid reliability and unified drivers, and "4 hours of battery life with <30min of charging", those 2 on their own make the wait worth it for me!repoman27 - Tuesday, July 30, 2019 - link
“The connection to the chipset is through a DMI 3.0 x4 link...”Should be OPI x8 for U/Y Series.
“...Ice Lake will support up to six ports of USB 3.1 (which is now USB 3.2 Gen 1 at 5 Gbps)...”
They’re USB 3.1 Gen 2 ports, so it’s six USB 3.2 Gen 2 x 1 (10 Gbit/s) ports.
Roel9876 - Tuesday, July 30, 2019 - link
Well, for one, it is certainly not realistic to run single thread benchmarks on application that support multi threading. Realistically, most (all?) people will run the application multi threaded?HStewart - Tuesday, July 30, 2019 - link
As developer for many years, multiple threads are useful for handling utility threads and such - but IO is typically area which still has to single thread. Unless it has significantly change in API, it is very difficult to multi-thread the actual screen. And similar for disk io as resource.Arnulf - Tuesday, July 30, 2019 - link
"Our best guess is that these units assist Microsoft Cortana for low-powered wake-on voice inference algorithms ..."Our best guess is that these are designed for use by assorted three-letter agencies.
PeachNCream - Tuesday, July 30, 2019 - link
Open mics are totally okay. There is absolutely no privacy risk to you at all and you should never give it a second thought.ToTTenTranz - Tuesday, July 30, 2019 - link
With 4x TB3 connections available, I wonder if the maker of an external GPU box could develop a multiplexer that combined two TB3 connections into a PCIe 3.0 8x.This would significantly decrease some problems that eGPU owners are having due to relatively low CPU-GPU bandwidth.