So what comes after 7nm, after 6nm, after 5nm, and after 4nm? That's right: 3nm! At Samsung's Foundry Forum event today, Samsung has announced that the first alpha version of its Product Design Kit for its first 3nm process is now ready for customers. What makes this announcement special is that 3nm is the intersection point where Samsung intends to introduce the next generation of Gate-All-Around (GAA) technology that will replace FinFETs. 

Beyond the FinFET: Moving to Gate-All-Around

The main driver for innovation in logic-based process technologies over the past decade has been FinFETs. Compared to a standard planar transistor, the FinFET allowed for better performance and voltage scaling as the process node decreased, minimizing the negative aspects of transistor limitations. FinFETs work by increasing the contact area between the channel of the transistor and the gate by scaling in a vertical direction, allowing for faster switching times and higher current density compared to a planar design.

However, like planar transistors, FinFET transistors eventually reach a point where they cannot scale as process nodes shrink. In order to scale, that contact area between the channel and the gate needs to increase, and the way to do this is to use a Gate-All-Around (GAA) design. GAA adjusts the dimensions of the transistor to ensure that the gate is also below the channel, not only on the top and the sides. This allows a GAA design to stack transistors vertically, rather than laterally.

GAA based FETs (GAAFETs) can come in a variety of form factors. Most of the research has pointed to nanowire based GAAFETs, with a small channel width and making the channel as small as possible. These type of GAAFETs are typically useful for low power designs, but are hard to manufacture. The other implementation is making the channel like a horizontal sheet, increasing the volume of the channel, which affords benefits towards performance and scaling. This nano-sheet based GAAFET is what Samsung is calling a Multi-Bridge Channel FET, or MBCFET, which is going to be a trademarked name for the company.

Where planar transistors scaled to around 22nm/16nm, FinFETs have been ideal as we go down from 22nm/14nm to 5nm and 4nm. Samsung is planning to introduce nano-sheet based GAAFETs on its 3nm design, replacing FinFETs entirely.

Building on 3nm: PDKs

When a semiconductor company designs a new chip on a given process, one of the tools they need is a design kit from the foundry then plan to use. For anyone creating an Arm chip on 14nm chip today for example, they would call up Arm and ask for the Cortex-A55 design kit for Samsung or TSMC or GlobalFoundries, which has been optimized for that process. For 14nm, these design kits are very mature, and Arm is likely to offer different versions depending if you want a high frequency or a low power optimization.

However when a process technology is new, early alpha and beta versions of these product design kits (PDKs) become available. The PDK contains the design rules for the process, as well as optimizations that are used to make the best for power and performance.  Typically the foundry will update the PDK as more chips are produced and more variations are tested to help its customers make the best chips.

The Nuance with MBCFETs

One of the features of MCBFETs that wasn’t specifically listed in Samsung’s press release is that nano-sheet based FETs are extremely customizable. The width of the nanosheet is a key metric in defining the power and performance characteristics: the higher the width, the higher the performance (at higher power). Samsung has included in its PDK four different nanosheet widths in order to provide co-optimization within the same chip design: transistor designs that focus on low power can use smaller nanosheets, while logic that requires higher performance can go for the wider sheets, but ultimately it's a continuous scale. By contrast, FinFETs only have one power/frequency design point within a process node design for a given fin count, creating only discrete profiles possible.

Samsung states that its 3GAE design, regardless of the sheet width design required, will allow for direct IP porting from any of its 4nm family designs. 3GAE and 4LPP share the same BEOL design rules, enabling this.

Samsung Announces 3nm GAA MBCFET PDK, Version 0.1

Today’s announcement is that Samsung is offering its first alpha version of the PDK for its first generation 3nm process that uses MBCFETs. Samsung is calling this process its ‘3GAE’ process, and this alpha version will allow its partners to start getting to grips with some of the new design rules for its 3GAE process.

Samsung is making a lot of promises with its first 3GAE process. One of the headlines is lowering the operating voltage from 0.75 volts to 0.70 volts, which will be a good step in power. The headline PPA values that Samsung is announcing are also impressive: compared to 7nm, 3GAE will offer 1.35x performance, 0.5x power, with a 0.65x die area.

Samsung states that these performance numbers are based on using larger width cells for critical paths where frequency is important, and smaller width cells for non-critical paths where power savings are crucial. Technically Fmax of the widest cells is listed as 1.5x, while power at Fmax is 0.6x. Power at iso-performance is where the 0.5x number comes from.

To put some of this in perspective: Samsung expects its 3GAE process to offer first customer tapeouts in 2020, with risk production in late 2020 and volume manufacturing in late 2021.

Beyond 3GAE, Samsung has already outlined that its second generation 3nm process will be called 3GAP, with a focus on high performance operation. The 3GAP process will be optimization focused, taking advantage of what Samsung has learned from 3GAE. 3GAE will go into risk production in 2021, with mass production likely in 2022.

PDK Tools and EDA Partners

For those that are interested, the PDK tools includes SPICE, DRC, LVS, PEX, P-Cell, Fill Deck, and P&R Techfile. EDA Partners include Cadence, Mentor, and Synopsis.

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  • Diogene7 - Wednesday, May 15, 2019 - link

    I am wondering if those improvements are available all at the same time, or only separately one by one ?

    Ex:
    1. Is it up to 35% performance improvement, OR up to 50% power decrease, OR up to 45% die area reduction ?

    2. Is it for example 35% performance improvement, but in that case, there is no or little power decrease and there is no or little die area shrink ?
    Reply
  • smilingcrow - Wednesday, May 15, 2019 - link

    In other such releases it always seems to be OR and never AND. Reply
  • saratoga4 - Wednesday, May 15, 2019 - link

    Power is nonlinear with performance, so 50% power decrease at isofrequency will mean a smaller decrease at higher frequency. Reply
  • valinor89 - Wednesday, May 15, 2019 - link

    It is funny when #SFF2019 is the tag for both the samsung event and a film festival. Reply
  • wrkingclass_hero - Thursday, May 16, 2019 - link

    It's crazy, there was this standstill at 28nm, and another one at 14nm where it seemed like any further improvements would be minimal, yet here we are in a whirlwind of constant developments that seem to be coming faster and faster. Reply
  • s.yu - Thursday, May 16, 2019 - link

    Not really, apparently 7nm would be 4x the density of 14nm right, that didn't happen, and this 3nm is not ~5.4x density of 7nm.
    The numbers are bumping, that's for sure.
    Reply

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