Going Beyond Gen11: Announcing the XE Discrete Graphics Brand

Not content with merely talking about what 2019 will bring, we were given a glimpse into how Intel is going to approach its graphics business in 2020 as well. It was at this point that Raja announced the new product branding for Intel’s discrete graphics business:

Intel will use the Xe branding for its range of graphics that were unofficially called ‘Gen12’ in previous discussions. Xe will start from 2020 onwards, and cover the range from client graphics all the way to datacenter graphics solutions.

Intel actually divides this market up, showing that Xe also covers the future integrated graphics solutions as well. If this slide is anything to go by, it would appear that Intel wants Xe to go from entry to mid-range to enthusiast and up to AI, competing with the best the competition has to offer.

Intel stated that Xe will start on Intel’s 10nm technology and that it will fall under Intel’s single stack software philosophy, such that Intel wants software developers to be able to take advantage of CPU, GPU, FPGA, and AI, all with one set of APIs. This Xe design will feed the foundation of several generations of graphics, and shows that Intel is now ready to rally around a brand name moving forward.

There was some confusion with one of the slides, as it would appear that Intel might be using the new brand name to also refer to some of it's FPGA and AI solutions. We're going to see if we can get an answer on that in due course.

Demonstrating Sunny Cove and Gen11 Graphics Changing How Chips are Made: 3D Packaging with FOVEROS
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  • f1nalpr1m3 - Wednesday, December 12, 2018 - link

    Yeah, they totally put it together in three weeks and everything.

    Get a clue.
    Reply
  • pkgtech - Thursday, December 20, 2018 - link

    For years Sohail Ahmed was the roadblock to Intel doing any creative package technology by blocking silicon support. He finally was shown for what he was after 2+ year process technology delays and re-invented this. Good riddance Sohail Reply
  • Adonisds - Wednesday, December 12, 2018 - link

    How do the Intel process delays influence their microarchitecture plans? 10 nm was already supposed to be here and with it its new microarchitecture, Ice Lake. Does the Ice Lake design continue to get improved as the delays kept happening or was it finalized years ago? Why? What about the microarchutectures succeeding Ice Lake? Reply
  • III-V - Wednesday, December 12, 2018 - link

    This is Ice Lake. Might be a 14nm port (unclear at this point why the name change), but it's at the very least a close relative. Reply
  • III-V - Wednesday, December 12, 2018 - link

    Actually, given the name on the heat sink, it is probably just straight up Ice Lake Reply
  • HStewart - Thursday, December 13, 2018 - link

    I believe the road map states Ice Lake will be on 10nm. More importantly it will be on Sunny Cove which is significant update to Architexture. Reply
  • AdhesiveTeflon - Wednesday, December 12, 2018 - link

    Intel and their naming scheme....they should call one "blue slushie lake" Reply
  • prisonerX - Wednesday, December 12, 2018 - link

    Plans? Intel are in full scale panic mode right now. I'm sure they have new plans every week. Reply
  • jjj - Wednesday, December 12, 2018 - link

    LOL you went in full fanboy mode with the 144mm package being small.
    The package is that size for PoP, the die is much much smaller, they can fit way more 10nm cores than that in such a large area, even without a base die.
    Anyway, there are no relevant details on Foveros and that's problematic. The first question is cost, then you would want to know details about pitch and so on. Intel is by no means the first to announce such a solution so the details are what matters.
    This is how you get to a 3D monolithic die in some years so any foundry that wants to stay in the most advanced node game, needs to push the packaging roadmap.
    Reply
  • Ian Cutress - Wednesday, December 12, 2018 - link

    I specifically said the package was small, and the die was smaller than the package. Reply

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