Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review
by Ian Cutress on January 25, 2019 10:30 AM ESTCPU Performance: SPEC2006 at 2.2 GHz
Aside from power, the other question is if the Cannon Lake microarchitecture is an efficient design. For most code paths, it holds the same core design elements as Skylake and Kaby Lake, and it does have additional optimizations for certain instructions, as we detailed earlier in this review. In order to do a direct IPC comparison, we are running SPEC2006 Speed on both of our comparison points at a fixed frequency of 2.2 GHz.
In order to get a fixed frequency on our chips required adjusting the relevant registers to disable the turbo modes. There is no setting in the BIOS to do this, but thankfully the folks at AIDA64 have a tool to do this and it works great. Choosing these two processors that both have a base frequency of 2.2 GHz make this a lot easier.
SPEC2006 is a series of industry standard tests designed to help differentiate performance levels between different architectures, microarchitectures, and compilers. All official submitted results from OEMs and manufacturers are posted online for comparison, and many vendors try and get the best results. From our perspective, these workloads are very well known, which enables a good benchmark for IPC analysis.
Credit for arranging the benchmarks goes completely to our resident Senior Mobile Editor, Andrei Frumusanu, who developed a suitable harness and framework to generate the relevant binaries for both mobile and PC. On PC, we run SPEC2006 through the Windows Subsystem for Linux – we still need to do testing for overhead (we’ll do it with SPEC2017 when Andrei is ready), but for the purposes of this test today, comparing like for like both under WSL is a valid comparison. Andrei compiled SPEC2006 for AVX2 instructions, using Clang 8. We run SPEC2006 Speed, which runs one copy of each test on one thread, of all the integer tests as well as the C++ based floating point tests.
Here are our results:
| SPEC2006 Speed (Estimated Results)* |
|||||
| Intel Core i3-8121U 10nm Cannon Lake |
AnandTech | Intel Core i3-8130U 14nm Kaby Lake |
|||
| Integer Workloads | |||||
| 24.8 | 400.perlbench | 26.1 | |||
| 16.6 | 401.bzip2 | 16.8 | |||
| 27.6 | 403.gcc | 27.3 | |||
| 25.9 | 429.mcf | 28.4 | |||
| 19.0 | 445.gobmk | 19.1 | |||
| 23.5 | 456.hmmr | 23.1 | |||
| 22.2 | 458.sjeng | 22.4 | |||
| 70.5 | 462.libquantum | 75.4 | |||
| 39.7 | 464.h264ref | 37.2 | |||
| 17.5 | 471.omnetpp | 18.2 | |||
| 14.2 | 473.astar | 14.1 | |||
| 27.1 | 483.xalancbmk | 28.4 | |||
| Floating Point Workloads | |||||
| 24.6 | 433.milc | 23.8 | |||
| 23.0 | 444.namd | 23.0 | |||
| 39.1 | 450.soplex | 37.3 | |||
| 34.1 | 453.povray | 33.5 | |||
| 59.9 | 470.lbm | 68.4 | |||
| 43.2 | 482.sphinx3 | 44.2 | |||
* SPEC rules dictate that any results not verified on the SPEC website are called 'estimated results', as they have not been verified.
By and large, we actually get parity between both processors on almost all the tests. The Kaby Lake processor seems to have a small advantage in libquantum and lbm, which are SIMD related, which could be limited by the memory latency difference shown on the previous page.
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qcmadness - Saturday, January 26, 2019 - link
I am more curious on the manufacturing node. Zen (14 / 12nm from GF) has 12 metal layers. Cannon Lake has 13 metal layers, with 3 quad-patterning and 2 dual patterning. How would these impact the yield and manufacturing time of production? I think the 3 quad-patterning process will hurt Intel in the long run.KOneJ - Sunday, January 27, 2019 - link
More short-run I would say actually. EUV is coming to simplify and homogenize matters. This is a patch job. Unfortunately, PL analysis and comparison is not an apples-to-apples issue as there are so many facets to implementation in various design stages. A broader perspective that encompasses the overall aspects and characteristics is more relevant IMHO. It's like comparing a high-pressure FI SOHC motor with a totally unrelated low-pressure FI electrically-spooling DOHC motor of similar displacement. While arguing minutiae about design choices is interesting to satisfy academic curiosity, it's ultimately the reliability, power-curve and efficiency that people care about. Processors are much the same. As a side note, I think it's the attention to all these facets and stages that has given Jim Keller such consistent success. Intel's shaping up for a promising long-term. The only question there is where RISC designs and AMD will be when the time comes. HSA is coming, but it will be difficult due to the inherent programming challenges. Am curious to see where things are in ten or fifteen years.eastcoast_pete - Sunday, January 27, 2019 - link
Good point and question! With the GPU functions apparently simply not compatible with Intel's 10 nm process, does anyone here know if any GPUs out there that use quad-patterning at all?anonomouse - Sunday, January 27, 2019 - link
@Ian or @Andrei Is dealII missing from the spec2006fp results table for some reason? Is this just a typo/oversight, or is there some reason it's being omitted?KOneJ - Sunday, January 27, 2019 - link
Great write up, but isn't this backwards on the third page?"a 2-input NAND logic cell is much smaller than a complex scan flip-flop logic cell"
"90.78 MTr/mm^2 for NAND2 gates and 115.74 MTr/mm^2 for Scan Flip Flops"
NAND cell is smaller than flip-flop cell, but there is more flip-flop than NAND in a square millimeter?
Or am I missing something?
Rudde - Sunday, January 27, 2019 - link
A NAND logic cell consists of 2 transistors, while a Scan flip flop logic cell can consist of different count of transistors depending on where it is used. If I remeber correctly, Intel uses 8, 10 and 12 transistor designs.That gives 45.39 million NAND cells per mm² (basically SRAM) and ~12 million flip-flop cells.
The NAND cell is smaller because it consists of fewer transistors.
KOneJ - Sunday, January 27, 2019 - link
It would be great if you guys could get a CNL sample in the hands of Agner Fog. He might be able to answer some of the micro-architecture questions through his tests.dragosmp - Sunday, January 27, 2019 - link
Awesome review, great in depth content and well explained. Considering the amount of work this entailed, it's clear why these reviews don't happen every day. Thanksdragosmp - Sunday, January 27, 2019 - link
I'll just add...many folks are saying AMD should kick arse. They should, but Intel has been in this situation before - they had messed up the 90nm process; probably not quite as bad as the chips to be unusable, but it opened the door to AMD and its Athlon 64. What did AMD do? Messed it up in turn with slow development and poor design choices. Hopefully they'll capitalize this time so that we get an actual dupoloy, rather than the monopoly on performance we had since Intel's 65nm chips.eva02langley - Sunday, January 27, 2019 - link
Euh... You mean this...?https://www.youtube.com/watch?v=osSMJRyxG0k
Anti-competitive tactics? They bought the OEM support to prevent competition.
And, all lately, this came up...
https://www.tomshardware.com/news/msi-ceo-intervie...
"Relationship with Intel: Chiang told us that, given Intel's strong support during the shortage, it would be awkward to tell Intel if he chose to come out with an AMD-powered product. "It's very hard for us to tell them 'hey, we don't want to use 100 percent Intel,' because they give us very good support," he said. He did not, however, make any claims that Intel had pressured him or the company."
Yeah right, Intel is winning because they have better tech... /sarcasm