Pricing Comparison: AMD versus Intel

We are all hoping that the renewed competition between Intel and AMD results in more bang for the buck. Intel just launched about 50 SKUs, so we made a list of those that will go head-to-head with AMD's already announced EPYC SKUs. On average, the Intel SKUs will priced slightly higher, reflecting the fact that Intel believes buyers are willing to pay a bit more for the vendor with the better track record. 

AMD EPYC Processors (2P) Intel Xeon Processoors (2-8P)
AMD EPYC
SKU
Cores
 
Freq
(GHz)
Base-Max
Price  Intel Xeon
SKU
Cores Freq 
(GHz)
Base-Max
Price
        Xeon 8180 (205W) 28 2.5-3.8 $10009
        Xeon 8176M (165W) 28 2.1-3.8 $11722
        Xeon 8176 (165W) 28 2.1-3.8 $8719
EPYC 7601
(180W)
32  2.2 -3.2 $4200 Xeon 8160 (150W) 24 2.1-3.7 $4702
EPYC 7551
(180W)
32 2.0-3.0 >$3400 Xeon 6152 (140W) 22 2.1-3.7 $3655
EPYC 7501 (155/170W) 32 2.0-3.0 $3400 Xeon 6150 (165W) 18 2.7-3.4 $3358
EPYC 7451
(180W)
24 2.3-3.2 >$2400 Xeon 6140 (165W) 18 2.3-3.7 $2445
EPYC 7401 (155/170W) 24 2.0-3.0 $1850 Xeon 6130 (125W) 16 2.1-3.7 $1894
        Xeon 5120 (105W) 14 2.2-3.2 $1555
EPYC 7351 (155/170W) 16 2.4-2.9 >$1100 Xeon 5118 (105W) 12 2.3-3.2 $1221
EPYC 7301 (155/170W) 16 2.2-2.7 >$800 Xeon 4116
(85W)
12 2.1-3.0 $1002
EPYC 7281 (155/170W) 16 2.1-2.7 $650 Xeon 4114
(85W)
10 2.2-3.0 $694
EPYC 7251
(120W)
2.1-2.9 $475 Xeon 4110
(85W)
8 2.1-3.0 $501

Several trends pop up as we look at the table above. 

First of foremost, those 24-28 core CPUs are a wonder of modern multicore CPU architecture, but you sure have to pay a lot of money for them. This is especially the case for the SKUs that can support 1.5 TB per socket. Of course if you can afford SAP Hana, you can afford $10k CPUs (or so the theory goes).

Still, if we compare the new high-end Skylake-EP SKUs with the previous 22-core Xeon E5-2699 v4 ($4199), paying twice as much for a 28-core chip just because it can be used in 8 socket configuration is bad news for those of us who need a very fast 2 socket system. In fact, it is almost as Intel has no competition: we only get a little more performance for the same price. For example you can get a Xeon 6148 (20 cores at 2.4 GHz, 150W TDP) for $3072, while you had to pay $3228 last generation for a Xeon E5-2698 v4 (20 cores at 2.2 GHz, 135W). The latter had smaller L2-caches but a much larger L3-cache (45 MB vs 27.5 MB). We're still not getting big steps forward on a performance-per-dollar basis, a similar problem we had with the launch of the Xeon E5 v4 last year. 

Hopefully, AMD's EPYC can put some pressure on Intel, if not exceed the 800lb gorilla entirely. AMD typically offers many more cores for the same price. At the high end, AMD offers up to 10 more cores than the similar Xeon: compare the EPYC 7551 with the Intel Xeon 6152.

On the other hand, Intel offers lower TDPs and higher turbo clocks. The 16-core EPYC CPUs in particular seem to have remarkably high TDPs compared to similar Intel SKUs. Those 16-cores look even worse as, despite the lower core count and high TDP, the turbo clock is lower than 3 GHz. 

In a nutshell: looking at the current lineups we want lower prices from Intel, and more attractive mid-range SKUs from AMD. 

AMD EPYC Processors (1P)
  Cores
Threads
Frequency (GHz) TDP Price
EPYC 7551P 32 / 64 2.0 -3.0 180W $2100
EPYC 7401P 24 / 48 2.0-3.0 155W/170W $1075
EPYC 7351P 16 / 32 2.4-2.9 155W/170W $750

Finally, AMD's single-socket SKUs – identified by a P suffix – are by far the most interesting to us and the most dangerous to Intel. It will be interesting to see how well two 12-core Xeon 5118s can compete with one EPYC 7551P. The clocks are similar, but AMD has 8 extra cores, a less complex server board, much more PCIe bandwidth, and a lower TDP.  AMD should have serious cost advantage on paper. We hope to check that in a later review.

Intel Expanding the Chipset: 10 GigE & QuickAssist Testing Notes & Benchmark Configuration
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  • oldlaptop - Thursday, July 13, 2017 - link

    Why on earth is gcc -Ofast being used to mimic "real-world", non-"aggressively optimized"(!) conditions? This is in fact the *most* aggressive optimization setting available; it is very sensitive to the exact program being compiled at best, and generates bloated (low priority on code size) and/or buggy code at worst (possibly even harming performance if the generated code is so big as to harm cache coherency). Most real-world software will be built with -O2 or possibly -Os. I can't help but wonder why questions weren't asked when SPEC complained about this unwisely aggressive optimization setting...
  • peevee - Thursday, July 13, 2017 - link

    "added a second full-blown 512 bit AVX-512 unit. "

    Do you mean "added second 256 ALU, which in combination with the first one implements full 512-bit AVX-512 unit"?
  • peevee - Thursday, July 13, 2017 - link

    "getting data from the right top node to the bottom left node – should demand around 13 cycles. And before you get too concerned with that number, keep in mind that it compares very favorably with any off die communication that has to happen between different dies in (AMD's) Multi Chip Module (MCM), with the Skylake-SP's latency being around one-tenth of EPYC's."

    1/10th? Asking data from L3 on the chip next to it will take 130 (or even 65 if they are talking about averages) cycles? Does not sound realistic, you can request data from RAM at similar latencies already.
  • AmericasCup - Friday, July 14, 2017 - link

    'For enterprises with a small infrastructure crew and server hardware on premise, spending time on hardware tuning is not an option most of the time.'

    Conversely, our small crew shop has been tuning AMD (selected for scalar floating point operations performance) for years. The experience and familiarity makes switching less attractive.

    Also, you did all this in one week for AMD and two weeks for Intel? Did you ever sleep? KUDOS!
  • JohanAnandtech - Friday, July 21, 2017 - link

    Thanks for appreciating the effort. Luckily, I got some help from Ian on Tuesday. :-)
  • AntonErtl - Friday, July 14, 2017 - link

    According to http://www.anandtech.com/show/10158/the-intel-xeon... if you execute just one AVX256 instruction on one core, this slows down the clocks of all E5v4 cores on the same socket for at least 1ms. Somewhere I read that newer Xeons only slow down the core that executes the AVX256 instruction. I expect that it works the same way for AVX512, and yes, this means that if you don't have a load with a heavy proportion of SIMD instructions, you are better off with AVX128 or SSE. The AMD variant of having only 128-bit FPUs and no clock slowdown looks better balanced to me. It might not win Linpack benchmark competitions, but for that one uses GPUs anyway these days.
  • wagoo - Sunday, July 16, 2017 - link

    Typo on the CLOSING THOUGHTS page: "dual Silver Xeon solutions" (dual socket)

    Great read though, thanks! Can finally replace my dual socket shanghai opteron home server soon :)
  • Chaser - Sunday, July 16, 2017 - link

    AMD's CPU future is looking very promising!
  • bongey - Tuesday, July 18, 2017 - link

    EPYC power consumption is just wrong. Somehow you are 50W over what everyone else is getting at idle. https://www.servethehome.com/amd-epyc-7601-dual-so...
  • Nenad - Thursday, July 20, 2017 - link

    Interesting SPECint2006 results:
    - Intel in their slide #9 claims that Intel 8160 is 2% faster than EPYC 7601
    - Anandtech in article tests that EPYC 7601 is 42% faster than Intel 8176

    Those two are quite different, even if we ignore that 8176 should be faster than 8160. In other words, those Intel test results look very suspicious.

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