SMT Integer Performance With SPEC CPU2006

Next, to test the performance impact of simultaneous multithreading (SMT) on a single core, we test with two threads on the same core. This way we can evaluate how well the core handles SMT. 

Subtest Application type Xeon E5-2690 @ 3.8 Xeon E5-2690 v3 @ 3.5 Xeon E5-2699 v4 @ 3.6 EPYC 7601 @3.2 Xeon 8176 @ 3.8
400.perlbench Spam filter 39.8 43.9 47.2 40.6 55.2
401.bzip2 Compression 32.6 32.3 32.8 33.9 34.8
403.gcc Compiling 40.7 43.8 32.5 41.6 32.1
429.mcf Vehicle scheduling 44.7 51.3 55.8 44.2 56.6
445.gobmk Game AI 36.6 35.9 38.1 36.4 39.4
456.hmmer Protein seq. analyses 32.5 34.1 40.9 34.9 44.3
458.sjeng Chess 36.4 36.9 39.5 36 41.9
462.libquantum Quantum sim 75 73.4 89 89.2 91.7
464.h264ref Video encoding 52.4 58.2 58.5 56.1 75.3
471.omnetpp Network sim 25.4 30.4 48.5 26.6 42.1
473.astar Pathfinding 31.4 33.6 36.6 29 37.5
483.xalancbmk XML processing 43.7 53.7 78.2 37.8 78

Now on a percentage basis versus the single-threaded results, so that we can see how much performance we gained from enabling SMT:

Subtest Application type Xeon E5-2699 v4 @ 3.6 EPYC 7601 @3.2 Xeon 8176 @ 3.8
400.perlbench Spam filter 109% 131% 110%
401.bzip2 Compression 137% 141% 128%
403.gcc Compiling 137% 119% 131%
429.mcf Vehicle scheduling 125% 110% 131%
445.gobmk Game AI 125% 150% 127%
456.hmmer Protein seq. analyses 127% 125% 125%
458.sjeng Chess 120% 151% 125%
462.libquantum Quantum sim 91% 129% 90%
464.h264ref Video encoding 101% 112% 112%
471.omnetpp Network sim 109% 116% 103%
473.astar Pathfinding 140% 149% 137%
483.xalancbmk XML processing 120% 107% 116%

On average, both Xeons pick up about 20% due to SMT (Hyperthreading). The EPYC 7601 improved by even more: it gets a 28% boost on average. There are many possible explanations for this, but two are the most likely. In the situation where AMD's single threaded IPC is very low because it is waiting on the high latency of a further away L3-cache (>8 MB), a second thread makes sure that the CPU resources can be put to better use (like compression, the network sim). Secondly, we saw that AMD core is capable of extracting more memory bandwidth in lightly threaded scenarios. This might help in the benchmarks that stress the DRAM (like video encoding, quantum sim). 

Nevertheless, kudos to the AMD engineers. Their first SMT implementation is very well done and offers a tangible throughput increase. 

Single Threaded Integer Performance: SPEC CPU2006 Multi-core SPEC CPU2006
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  • alpha754293 - Tuesday, July 11, 2017 - link

    Pity that OpenFOAM failed to run on Ubuntu 16.04.2 LTS. I would have been very interested in those results. Reply
  • farmergann - Tuesday, July 11, 2017 - link

    Are you trying to hide the fact that AMD's performance per watt absolutely dominates intel's, or have you simply overlooked one of, if not the, single most important aspects of server processors? Reply
  • Ryan Smith - Tuesday, July 11, 2017 - link

    Neither. We just had very little time to look at power consumption. It's also the metric we're the least confident in right now, as we'd like to have a better understanding of the quirks of the platform (which again takes more time). Reply
  • Carl Bicknell - Wednesday, July 12, 2017 - link

    Ryan / Ian,
    Just to let you know there are better chess benchmarks than the one you've chosen. Stockfish is an example of a newer program which better uses modern CPU architecture.
    Reply
  • NixZero - Tuesday, July 11, 2017 - link

    "AMD's MCM approach is much cheaper to manufacture. Peak memory bandwidth and capacity is quite a bit higher with 4 dies and 2 memory channels per die. However, there is no central last level cache that can perform low latency data coordination between the L2-caches of the different cores (except inside one CCX). The eight 8 MB L3-caches acts like - relatively low latency - spill over caches for the 32 L2-caches on one chip. "
    isnt skylake-x's l3 a victim cache too? and divided at 1.3mb for each core, not a monolytic one?
    Reply
  • Ian Cutress - Tuesday, July 11, 2017 - link

    That's what a 'spill-over' cache is - it accepts evicted cache lines. Reply
  • NixZero - Wednesday, July 12, 2017 - link

    so why its put as an advantage for intel cache, which is spill over too? Reply
  • JonathanWoodruff - Wednesday, July 12, 2017 - link

    Since the Intel one is all on one die, a miss to a "slice" of cache can be filled without DRAM-like latencies from another slice. Since AMD has it's last level caches spread across dies, going to another cache looks to be equivalent latency-wise to going to DRAM. It wouldn't necessarily have to be quite that bad, and I would expect some improvement here for Zen2. Reply
  • Martin_Schou - Tuesday, July 11, 2017 - link

    This has to be wrong:

    CPU Two EPYC 7601 (2.2 GHz, 32c, 8x8MB L3, 180W)
    RAM 512 GB (12x32 GB) Samsung DDR4-2666 @2400

    12 x 32 GB is 384 GB, and 12 sticks doesn't fit nicely into 8 channels. In all likelihood that's supposed to be 16x32 GB, as we see in the E52690
    Reply
  • Dr.Neale - Tuesday, July 11, 2017 - link

    I find myself puzzled by the curious omission in this article of a key aspect of Server architecture: Data Security.

    AMD has a LOT; Intel, not so much.

    I would think this aspect of Server "Performance" would be a major consideration in choosing which company's Architecture to deploy in a Secure Server scenario. Especially in light of Recent Revelations fuelling Hacking Headlines in the news, and Dominating Discussions on various social media websites.

    How much is Data Security worth?

    A topic of EPYC consequence!
    Reply

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