Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s 7 nm process technology, and is designed to enable SoC developers to begin on their DDR5 memory subsystems now and get them to market in 2019-2020, depending on high-volume DDR5 availability. At a special event, Cadence teamed up with Micron to demonstrate their DDR5 DRAM subsystem. In the meantime, Micron has started to sample its preliminary DDR5 chips to interested parties. DDR5-4400 Initially, DDR5-6400 Eventually Cadence’s DDR5 memory controller and PHY achieve a 4400 MT/s data rate with CL42 using Micron’s prototype 8 Gb DDR5 memory chips. Compared to DDR4 today, the supply voltage of DDR5 is...
Today we're taking a look at ADATA's Premier SP550 SSD, the company's latest entry-level drive. The Premier SP550 gives us a fresh look at Silicon Motion's SM2256 controller by...25 by Billy Tallis on 3/23/2016
Around a year ago DRAM manufacturers ended up pinning a lot of their hopes on DDR4 as a way to improve their profit margins. In the cutthroat and highly...16 by Anton Shilov on 2/25/2016
In Q4 2015, JEDEC (a major semiconductor engineering trade organization that sets standards for dynamic random access memory, or DRAM) finalized the GDDR5X specification, with accompianing white papers. This...70 by Anton Shilov on 1/22/2016
The high-bandwidth memory (HBM) technology solves two key problems related to modern DRAM: it substantially increases bandwidth available to computing devices (e.g., GPUs) and reduces power consumption. The first-generation...42 by Anton Shilov on 1/20/2016
Today we're launching a new feature on the AnandTech Pipeline: Price Check. Here we'll periodically examine hardware prices and analyze what's behind recent price changes. Just a year ago DDR4...33 by Anton Shilov on 12/18/2015
The workstation market has always been a consistent seller. The dream of offloading to an on or off-site VM and a cluster for work processing still lies more in...61 by Ian Cutress on 5/6/2015
The DRAM market, especially at the consumer level, is a cut and thrust business. Margins are small on a per-module basis, but with the right volume it can make...30 by Ian Cutress on 1/23/2015