Cadence has announced that it has successfully taped out its GDDR6 IP on Samsung’s 7LPP fabrication process. The new building blocks should enable developers of various chips to be made using 7LPP and quickly and easily integrate support of GDDR6 memory into their SoCs. Cadence’s GDDR6 IP solution includes the company’s Denali memory controller, physical interface, and verification IP. The controller and PHY are rated to handle up to 16 Gbps data transfer rates per pin and feature a low bit-error rate (BER) feature that decreases retries on the memory bus to cut-down latency and therefore ensure a greater memory bandwidth. The IP package is available as Cadence’s reference design that allows SoC developers to quickly replicate implementation that the IP designer used for its...
Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...18 by Anton Shilov on 10/17/2018
Cadence is an industry player we don’t mention nearly enough as much as we should - they make a lot of IP and specialises in accelerator blocks which augment...10 by Andrei Frumusanu on 9/19/2018
Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...31 by Anton Shilov on 5/3/2018
TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a...12 by Anton Shilov on 9/14/2017