In the realm of processor and product design, having the right series of tools to actually build and simulate a product has been a key driver in minimizing time to market. Cadence is one of the more prolific companies in the electronic design automation (EDA) software space, with tools for designing integrated circuits, PCBs, packaging, SoCs, radio frequency, as well as respective verification tools. What landed in my inbox this morning was an announcement for a new tool in Cadence’s solver portfolio to enable better full-system EM simulation while also scaling across CPU and GPU as well as to other systems. Cadence’s 3D Transient Solver uses a finite difference time domain model to essentially model an anechoic chamber over a wide frequency range for both...
JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which...20 by Anton Shilov on 3/27/2020
Samsung Foundry has certified full flow tools from Cadence and Synopsys for its 5LPE (5 nm low-power early) process technology that uses extreme ultraviolet lithography (EUV). Full flow design...13 by Anton Shilov on 7/8/2019
Cadence has announced that it has successfully taped out its GDDR6 IP on Samsung’s 7LPP fabrication process. The new building blocks should enable developers of various chips to be...11 by Anton Shilov on 11/26/2018
Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...18 by Anton Shilov on 10/17/2018
Cadence is an industry player we don’t mention nearly enough as much as we should - they make a lot of IP and specialises in accelerator blocks which augment...9 by Andrei Frumusanu on 9/19/2018
Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...31 by Anton Shilov on 5/3/2018
TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a...12 by Anton Shilov on 9/14/2017