Last year we saw the announcement of Cadence’s Tensilica Q6 DSP IP which promised a new architecture that brings integration between vision DSP workloads and new optimised machine learning inferencing workloads. The addition of “AI” capabilities to existing DSP architectures bridges the gap between existing IP blocks such as CPUs or GPUs and more specialised dedicated inferencing IP blocks such as Cadence’s own Tensilica DNA100 block. Today’s announcement is an evolution of last year’s Q6, further progressing the capabilities we saw introduced in the new architecture and enabling more performance, better density and better power efficiency. Over the next few years Cadence sees significant growth opportunity for the vision DSP market, with the overall image sensor market growing at a rate of ~12% CAGR till 2025...
Cadence has announced that it has successfully taped out its GDDR6 IP on Samsung’s 7LPP fabrication process. The new building blocks should enable developers of various chips to be...11 by Anton Shilov on 11/26/2018
Earlier this year Cadence and Micron performed the industry’s first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates...18 by Anton Shilov on 10/17/2018
Cadence is an industry player we don’t mention nearly enough as much as we should - they make a lot of IP and specialises in accelerator blocks which augment...9 by Andrei Frumusanu on 9/19/2018
Cadence this week introduced the industry’s first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence’s IP and test chip us fabricated using TSMC’s...31 by Anton Shilov on 5/3/2018
TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a...12 by Anton Shilov on 9/14/2017