45nm Awaits

Along with an update on shipments, Otellini's keynote today gave us a small update on Intel's manufacturing processes.

In the 2nd half of 2007, Intel will begin its transition to a 45nm manufacturing process. The 45nm version of today's Core 2 processors is codenamed Penryn and will be among the first chips to use Intel's new 45nm process. In addition to Penryn, there are 15 other 45nm processors that are currently in development, with the first design due to be complete in the next quarter.

Currently there's one 45nm fab up and running: Fab D1D in Oregon, which is producing test wafers now.

There are two more 45nm fabs under construction that will help the transition once they come online:

Once all three 45nm fabs are up and running the total investment will have been $9B and provide Intel with 0.5 million square feet of cleanroom.

Looking even further into the future the successor to Intel's Core architecture, codenamed Nehalem, will use its 45nm technology and by 2010 Intel's Gesher microarchitecture will be built on 32nm.

Halfway to 65nm Quad-Core in November
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  • GNStudios - Wednesday, September 27, 2006 - link

    Is Quad-core going to much faster than dual-core, like when core 2 duo came?

    Reply is appriciated. :-)
    Reply
  • Niv KA - Wednesday, September 27, 2006 - link

    I have reasons to belive that whatever will come after Gesher will be very different from what we have today. Gesher is translated to brigde in Hebrew. Therefore I have reason to belive that what ever Gesher will be, it will be a transition to a new technology.

    I know I repeated myself a few times.

    -- Niv K Aharonovich
    Reply
  • sprockkets - Wednesday, September 27, 2006 - link

    It used a Netburst and most likely a prescott core processor to operate WTF?

    Reply
  • GhandiInstinct - Wednesday, September 27, 2006 - link

    The day, in a press conference, the day in which multi-code is mastered in software, that we see in a video game demo, a full fledged Torando tearing down a metropolis. Reply
  • yacoub - Tuesday, September 26, 2006 - link

    Good coverage so far: Lots of pics, informative text between them, and lots of new tech incoming from Intel! woot Reply
  • porkster - Tuesday, September 26, 2006 - link

    Any news on Santa Rosa chipsets? I couldn't see them in the road map. Reply
  • porkster - Tuesday, September 26, 2006 - link

    Intel and Microsoft have no idea when it comes to what people will buy and can afford.

    Ye, like in the picture we are all going to buy 3 and 4 of these flop devices for our cars. Without these devices being under $200, no one will take then serious.

    It seems like anytime someone bring up a portable, they have to use an expensive cpu in it. I can't see why you can't jsut echo a wifi'ed screen from another computer at home or in the car. A device the is a terminal, not a separate computer.
    Reply
  • mino - Tuesday, September 26, 2006 - link

    "Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

    IBM has it since 2002 ... ;)

    BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

    That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

    First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.
    Reply
  • mino - Tuesday, September 26, 2006 - link

    "Years ago Micron talked about equipping a chipset with an on-die L3 cache to help improve performance, and it's looking like Intel will be doing just that"

    IBM has it since 2002 ... ;)

    BTW it was the main reason IMB did not jump on Opteron so eagerly. They have a chipset hugely hugely superior to Itel's Truland since 2003. Game over period.

    That snoop cache is the thing which brought SC Nocona Xeons on par with SC Opterons in 4P-8P scenarios!!!

    BTW First Intel DC Smithfield _IS_ single-die, it is just glued together but single-die. The reason being MCM puts huge strain on FSB so they put an arbitter on a glued chip, to help achieve even mediocre 800FSB on their chipsets of the time.
    Reply
  • mino - Tuesday, September 26, 2006 - link

    screwed title, if posiible please delete/vote out. Thanks. Reply

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