Intel Made Something Really Funny

Q&A with Raja, Jim, and Murthy

Through Intel’s Architecture Day, the company did a couple of side discussions for a few journalists to speak to Raja Koduri and Jim Keller in a round-table format. Beyond that, Murthy Renduchintala and Raja also held a Q&A session at the end of the day. They answered questions on 10nm, the new Foveros technology, Thunderbolt 3 adoption, and how Intel will approach 5G.

For this article, the Questions and Answers will be listed as an abridged version of the responses, due to time constraints and live transcription, with questions grouped based on topic. Different members of the press asked these questions.


Raja Koduri

Jim Keller

Dr. Murthy Renduchintala
Chief Architect 
Senior VP
Core and Visual Computing Group
Senior VP 
Silicon Engineering Group
Chief Engineering Officer
Group President, Technology, Systems Architecture & Client Group

 

Q: A lot of the CPU microarchitecture at Intel has been hamstrung by delays on process node technology. What went wrong, and what steps have been made to make sure it doesn't happen again?

R/J: Our products will be decoupled from our transistor capability. We have incredible IP at Intel, but it was all sitting in the 10nm process node. If we had had it on 14nm then we would have better performance on 14nm. We have a new method inside the company to decouple IP from the process technology. You must remember that customers buy the product, not a transistor family. It’s the same transformation AMD had to go through to change the design methodology when they were struggling. At Apple it was called the ‘bus’ method.

M: This is a function of how we as a company used to think about process node technologies. It was a frame tick (limiting factor) for how the company moved forward. We've learned a lot about how this worked with 14nm. We now have to make sure that our IP is not node-locked. The ability to have portability of IP across multiple nodes is great for contingency planning. We will continue to take aggressive risks in our designs, but we also will have contingency. We need to have as much of a seamless roadmap as possible in case those contingencies are needed, and need to make sure they are executed on ASAP if needed to keep the customer expectations in line. You will see future node technologies, such as 10/7, have much more overlap than before to keep the designs fluid. Our product portfolio on 14nm could have been much better if our product designs were not node-locked to 10nm.

R: In the future there will be no transistor left behind, no customer left behind, and no IP left behind.

Q: Will we ever see a 10nm monolithic desktop CPU at the high end?

R: Yes.

Q: How is 10nm? Has it changed?

R: It is changing, but it hasn't changed. There are a lot of lessons learned in how Intel approached it to begin with. We are established a much better model between manufacturing and design. We want good abstractions in product and process node going forward. When everything was going well, this issue didn't manifest and so wasn't an issue. There's complexity here when something bad happens on process, so the whole pipeline clogs up - the rest of the world solves this with abstraction. We need to make sure it won't happen again, and we have a desire to build resilience in the roadmap.

Q: Are there plans for mixed SoCs, combining CPU / GPU / AI / FPGA ?

R: In our roadmap there will be scalable vector/matrix combinations. What our customers want are very scalable solutions. Customers want similar programming models regardless of the silicon.

 

Q: What has been the effect of hiring Raja/Jim and bringing outsiders to Intel?

M: Intel is very innovative. We want to add to that chemistry and make sure we bring in people who understand Intel but also bring in good ideas. It's about respecting the rest of the market and make sure Intel is competitive. It's balancing the centre of internal debates by making sure we are challenging internal beliefs and the status quo by bringing in people who have done this sort of thing before. It shows to Intel's strengths in its ability to absorb interesting ideas from the outside. We went for the very best on the outside because that was what required to join with the very best on inside.

Q: What is Intel’s current approach to 5G, given the topics discussed today?

M: We think about 5G from the datacentre to the network to the edge and to the device. We at Intel believe the transition to 5G and its implications on the network, in terms of accelerating data and catalysing a software defined network where bespoke silicon gets replaced by containers, is as transformative as the jump from analogue to digital. It will accelerate the ‘cloudification’ of the network. The edge is important, especially to minimize latency for new services. Sub-millisecond latency for these services is critical. The over-the-air interface is important too. The intelligent cloud domain is going to be the flywheel about how fast the industry evolves. We mentioned in November that our XMM 5G modem will be in the hands of partners in the second half of 2019 with products in early 2020. It is a multi-mode 5G LTE architecture from day one, supporting all 3 mmWave bands, and sub-6 GHz frequencies.

 

Q: As Thunderbolt 3 requires additional chips, how do you see future OEM adoption?

M: Integrated Type-C Thunderbolt 3 is the first generation. We will refine it in the future - that's the natural genealogy of the technology. We constantly think about how much we integrate into the chip and how much we leave on the board.

R: This is a big IP challenge, not only for TB3, but for other IP. Integrated PHYs are important. For example, by disaggregating the transceiver in our FPGA line-up, it has allowed us to focus on that decoupled IP a lot.

Q: In the demo of FOVEROS, the chip combined both big x86 cores built on the Core microarchitecture and the small x86 cores built on the Atom microarchitecture. Can we look forward to a future where the big and little cores have the same ISA?

R: We are working on that. Do they have to have the same ISA? Ronak and the team are looking at that. However I think our goal here is to keep the software as simple as possible for developers and customers. It's a challenge that our architects have taken up to ensure products like this enter the market smoothly. We’ll also have a packaging discussion next year on products like this. The chip you see today, while it was designed primarily for a particular customer to begin with, it’s not a custom product, and in that sense will be available to other OEMs.

M: We've made the first step on a journey. That first step is a leap, and the next step is incremental. As we've said about One API strategy – if we homogenise the API then it'll go into all our CPUs. FOVEROS is also a new part/product that shows that we had a gap in our portfolio – it has helped us create technologies to solve an issue and we expect to expand on this in the future with new IP.

Q: Are you having fun with FOVEROS?

J: Because Raja deals in GPUs, he’s having fun with high bandwidth communications between compute elements. It's a new technology and we're having some experimentation with it. What is frustrating is that as an industry we hit a limit for current flux density a year before stacking technology became viable, so for high performance on stacking we're trying a lot of things in different areas. There's no point having to make thermal setbacks if it also removes the reason why you're using the technology. But we're having fun and trying a lot, and we'll see FOVEROS in a number of parts over the next 5 years. We will find new solutions to problems we don't even know exist yet.

Q: When is Manufacturing Tech Day?

M: We will tell you when it happens! I'm sure you all have opinions on Intel 10nm right now and yes we are looking at what we're doing, eating an amount of humble pie, but we're re-adjusting our process to make sure that we can take the best process no matter what the product is.

The title of this page was a quote from Jim during the Q&A: 'At some point in the future you'll read an article with the title Intel Made Something Really Funny.'. I think I win this bet...

Ice Lake 10nm Xeon Scalable On Display
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  • nathanddrews - Wednesday, December 12, 2018 - link

    I know the meme about gaming on Intel graphics, but if they implement Adaptive Sync *combined* with some sort of low framerate compensation, it would make gaming on Intel IGP much less hilarious. Can Intel license FreeSync without using AMD GPU inside? I know FreeSync worked on KLG, but that had an AMD GPU. Reply
  • RarG123 - Wednesday, December 12, 2018 - link

    Like many of AMD's things, FS's an open standard and royalty free. Anyone can use it. Reply
  • Ryan Smith - Wednesday, December 12, 2018 - link

    More specifically, Freesync 1 just AMD's implementation of DisplayPort Adaptive Sync. Intel has to build their own implementation in their display controller and driver stack, but past that all the signaling aspects to the monitor are standardized. Reply
  • Topweasel - Wednesday, December 12, 2018 - link

    Ryan, I thought that was reversed, that AMD worked on adding Adaptive Sync into the specs and worked on making sure it's implementation matched what they were doing with Freesync. Reply
  • kpb321 - Wednesday, December 12, 2018 - link

    IIRC it's a bit of both. Adaptive Sync was present in the eDP standard for things like laptop monitors or tablets as a power saving feature. AMD brought this to the desktop side of things to use for variable framerates in games and helped the standard bring it over too. Reply
  • edzieba - Wednesday, December 12, 2018 - link

    'Adaptive Sync' is effectively the eDP Panel Self Refresh ported over to the full DP spec. Reply
  • drunkenmaster - Wednesday, December 12, 2018 - link

    Freesync utilises adaptive sync. Adaptive Sync is the technology on the screen side, a screen must support adaptive sync to be used by Freesync. Freesync is just the AMD side of it. If a adaptive sync capable screen is detected you can turn on freesync in drivers. Adaptive sync was a standard written up and proposed by AMD and given to I forget who it is now, Displayport group direct or to Vesa. They accepted it and implemented it pretty quickly but as with all things standards take a long time for get integrated into the next cycle or two of products.

    Anyone can use Adaptive sync panels, no one but AMD can use freesync as it's something specific to their hardware and drivers. intel will produce their own specific driver/implementation and just connected to adaptive sync panels in the same way.
    Reply
  • porcupineLTD - Wednesday, December 12, 2018 - link

    So Intel is going straight to chiplets on interposer, it will be interesting to see if AMD adopts this with Zen 3 or waits until Zen 4. Anyway its nice to see competition doing its job. Reply
  • Alexvrb - Wednesday, December 12, 2018 - link

    We don't know yet exactly how much logic Intel is moving to the interposer. It looks awesome for mobile form factors! I think they will face some challenges to bring it to high-TDP desktop solutions, though. Reply
  • ajc9988 - Wednesday, December 12, 2018 - link

    http://www.eecg.toronto.edu/~enright/micro14-inter... http://www.eecg.toronto.edu/~enright/Kannan_MICRO4... https://youtu.be/G3kGSbWFig4 https://seal.ece.ucsb.edu/sites/seal.ece.ucsb.edu/... https://www.youtube.com/watch?v=d3RVwLa3EmM&t=... Reply

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