Manufacturing: Making Wafers

To make a computer chip, it all starts with the Czochralski process. The first step of this process is to take extremely pure silicon and melt it in a crucible that is often made of quartz. Doping material can also be added at this stage, to change the properties of the final crystal. Once this is done, a single seed crystal is dipped into the molten silicon, then carefully pulled up with a specific rotation rate. This produces a piece of monocrystalline silicon that is then sliced into wafers. These wafers can be up to 300mm in diameter at present and around .75mm thick, and they are polished to ensure that the surface is as regular and flat as possible.

Manufacturing: Photolithography/FEOL

Photolithography Etching Process / Cmglee / CC BY SA
Scanning Stepper Middle Exposure / Everyguy

Once this is done, the wafer is prepared for photolithography. An oxide layer on top of the silicon wafer is grown, and then the entire wafer is cleaned to remove contaminants. Once this is done, an adhesion promoter is applied to ensure that the photoresist will stick properly to the wafer. The photoresist is then applied by dispensing a solution of photoresist on to the wafer. The wafer is then spun at extremely high speeds for around half a minute to a minute. Once this is done, the wafer is then baked on a hot plate to get rid of the remaining solvent. In preparation for the exposure, a reticle/photomask for one layer of the process is loaded, and aligned with the wafer. In order to increase resolution, an exposure slit is used to optimize for a smaller exposure area on the reticle/projection lens system, and aberration is reduced.

Once all of this preparation is done, the exposure process begins. Intense UV light (currently 193nm) is used to change the exposed photoresist to allow the developer to strip away the exposed area. As a quick aside, the fact that UV light is used to develop the regions to etch away means that only long wavelength light can be used in clean rooms, which gives the clean room a characteristic yellow lighting. Once this is done, the wafer is baked again. This process is done again in order to properly develop the photoresist.

Once the wafer is ready, developer is added. This strips away the photoresist from the exposed regions. The exposed oxide is then etched away. While this process can be done with a liquid agent, modern dry-etch processes ionize a gas in vacuum using an RF cavity that is then shot at the exposed oxide to avoid etching past the exposed portion of the oxide. Once this etching process is complete, the photoresist is removed either through plasma ashing or by washing it off with a resist stripper.

To summarize everything I just said, the process is effectively cleaning the wafer, applying photoresist, exposing the photoresist, developing the photoresist, etching the exposed oxide, then removing the remaining photoresist.

CMOS Fabrication Process / Cmglee / CC BY SA

A modern wafer will undergo this process around 50 times or so before creating the final finished chip. You might want to know how all of this etching actually creates transistors, so we’ll once again go over the simplest case, the CMOS inverter. The first lithography pass is used to mark out the area so that we can deposit a well of n-doped silicon that the PMOS will use. Then, the oxide is grown again and a layer of polysilicon is deposited.

Another lithography pass is done to etch away parts of the oxide, then most of the polysilicon. This leaves a small piece in the center of the exposed substrate composed of silicon dioxide, then polysilicon. If this sounds familiar, it’s because this is the structure of the gate. Once this is done, ion implantation is used to create the sources and drains. The best description I can give of ion implantation is taking an ion and accelerating it to high speeds to embed itself into the targeted area, which dopes the substrate. Once this is done, a layer of nitride is added to prevent further oxide growth, which is then etched again.

Manufacturing: Back End of Line and Back End of Chip

Yet we’re still not done with how the chip is made. We just finished going over what happens in front-end-of-line (FEOL) processing. Now it’s time to go over what happens at back-end-of-line (BEOL) processing. Once the nitride layer is finished, a layer of metal is deposited over the entire system. This layer is then etched again to finish the transistor fabrication process. The result is that all the correct components for source, drain, gate, and body are implanted with metal connectors for input and output for our hypothetical CMOS inverter.

In a real chip, as many as 12 layers are added in this process, which means repeating the metal deposition step 12 times. This step is where all of the transistors are wired together, along with interlayer connections (vias), capacitors (in DRAM), dielectric isolation, and chip to package connectors. Once BEOL processing is complete, the chip is packaged and ready to be used.

CMOS Chip Structure / Cepheiden / CC BY SA

Of course, this entire production process isn’t perfect. Along the way, the wafer is tested multiple times to ensure that there are no defects from a previous step. If there are too many defects on a wafer, the entire wafer must be thrown away to avoid wasting time and money on further processing. After the FEOL processing is complete, the chip is tested and binned using a wafer prober. After the entire chip is packaged, the chip is tested again to ensure that the entire package is fully functional. The packaging and final testing stages are also known as the back end of chip fabrication.


To review everything we’ve just gone over, we started with the physics of semiconductors. Then we moved on to the physics of transistors. After that, we went over how to make logic with these transistors. Finally, we went over how to actually make transistors with logic. This would be a good place to stop, but complacency is a terrible reason to do so.

The question now is how to make things faster with less power. To do this, we have to figure out how to make the feature size smaller, in order to pack more transistors closer together. To put things in perspective, 43 years ago in 1971 with the Intel 4004 we had a feature size of 10,000 nanometers. That’s around 455 times as large as the 22nm feature size of what we see in Intel’s Haswell CPUs. Now it’s time to find out how this was achieved.

Transistors and CMOS Logic Shrinking Feature Size: Light Sources to OPC


View All Comments

  • Kristian Vättö - Saturday, October 11, 2014 - link

    Double (or more) patterning. Reply
  • EMM81 - Monday, October 13, 2014 - link

    Over the past 20 years many tricks have been developed to overcome what was originally believed to be an optical limitation. Lithography tools are much more complicated than the brief descriptions given and have had many advances including going from aligners->steppers->scanners, NA=1.35, illumination system improvements, resist improvements, anti-reflective coating improvements, different types of phase shift on all reticles... On top of the fact that we can resolve sub 50nm pitches with 193nm light we use various double patterning schemes. Reply
  • abufrejoval - Saturday, October 11, 2014 - link

    It's a wonderful article, something I'll quote and link to for a long time very much along the epochal piece Anand wrote on Flash.

    I'd like to see a followup or a mention to memristors, though. Not only because they are about to eliminate disk, flash, DRAM and SRAM, but because they also have such huge potential in FPGA and log redesign.

    On top their stacking capabilities together with the low energy density and production cost may actually allow attenuating the need for process shrinks to the point where it almost feels as though Moore's law was continuing, but not through process shrinks.
  • abufrejoval - Saturday, October 11, 2014 - link

    need edit!

    last two words on 2nd paragraph should read "logic redesign".
  • stimudent - Saturday, October 11, 2014 - link

    You won't find an article like this on childish websites like Tech Report. Reply
  • l_d_allan - Saturday, October 11, 2014 - link

    I don't find this an "Intro", but rather like a summary of EE 301 for people who have taken EE 101, EE 201, and EE 301. To me, it assumes a high level to prerequisites.
    Also, the article could benefit by more care taken to definitions ... for example, EUV is used repeatedly on the fourth page, but not defined until the sixth page.
  • The0ne - Saturday, October 11, 2014 - link

    "But there is far more to be done, as literally everything we write about at AnandTech depends upon ever faster, smaller, and more efficient transistors packed as tightly as possible. Without this continued innovation, the PC, smartphone, and wearables that we see today would be impossible to make."

    Thank you. Needed this article to remove the foul taste left my the recent iPhone reviews reasoning the phone is great because it can't improve any more.
  • Doomtomb - Monday, October 13, 2014 - link

    Awesome article. Great introduction to people curious about the industry. Some terms were glossed over that might help explain semiconductor physics more such as work function and crystal lattice, but there's only so much you can cover at once Reply
  • vermaasit - Monday, October 13, 2014 - link

    This was awesome article. Keep going Reply
  • DIYEyal - Monday, October 13, 2014 - link

    One of the best articles on this site. Good job! Reply

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