Manufacturing: Making Wafers

To make a computer chip, it all starts with the Czochralski process. The first step of this process is to take extremely pure silicon and melt it in a crucible that is often made of quartz. Doping material can also be added at this stage, to change the properties of the final crystal. Once this is done, a single seed crystal is dipped into the molten silicon, then carefully pulled up with a specific rotation rate. This produces a piece of monocrystalline silicon that is then sliced into wafers. These wafers can be up to 300mm in diameter at present and around .75mm thick, and they are polished to ensure that the surface is as regular and flat as possible.

Manufacturing: Photolithography/FEOL

Photolithography Etching Process / Cmglee / CC BY SA
Scanning Stepper Middle Exposure / Everyguy

Once this is done, the wafer is prepared for photolithography. An oxide layer on top of the silicon wafer is grown, and then the entire wafer is cleaned to remove contaminants. Once this is done, an adhesion promoter is applied to ensure that the photoresist will stick properly to the wafer. The photoresist is then applied by dispensing a solution of photoresist on to the wafer. The wafer is then spun at extremely high speeds for around half a minute to a minute. Once this is done, the wafer is then baked on a hot plate to get rid of the remaining solvent. In preparation for the exposure, a reticle/photomask for one layer of the process is loaded, and aligned with the wafer. In order to increase resolution, an exposure slit is used to optimize for a smaller exposure area on the reticle/projection lens system, and aberration is reduced.

Once all of this preparation is done, the exposure process begins. Intense UV light (currently 193nm) is used to change the exposed photoresist to allow the developer to strip away the exposed area. As a quick aside, the fact that UV light is used to develop the regions to etch away means that only long wavelength light can be used in clean rooms, which gives the clean room a characteristic yellow lighting. Once this is done, the wafer is baked again. This process is done again in order to properly develop the photoresist.

Once the wafer is ready, developer is added. This strips away the photoresist from the exposed regions. The exposed oxide is then etched away. While this process can be done with a liquid agent, modern dry-etch processes ionize a gas in vacuum using an RF cavity that is then shot at the exposed oxide to avoid etching past the exposed portion of the oxide. Once this etching process is complete, the photoresist is removed either through plasma ashing or by washing it off with a resist stripper.

To summarize everything I just said, the process is effectively cleaning the wafer, applying photoresist, exposing the photoresist, developing the photoresist, etching the exposed oxide, then removing the remaining photoresist.

CMOS Fabrication Process / Cmglee / CC BY SA

A modern wafer will undergo this process around 50 times or so before creating the final finished chip. You might want to know how all of this etching actually creates transistors, so we’ll once again go over the simplest case, the CMOS inverter. The first lithography pass is used to mark out the area so that we can deposit a well of n-doped silicon that the PMOS will use. Then, the oxide is grown again and a layer of polysilicon is deposited.

Another lithography pass is done to etch away parts of the oxide, then most of the polysilicon. This leaves a small piece in the center of the exposed substrate composed of silicon dioxide, then polysilicon. If this sounds familiar, it’s because this is the structure of the gate. Once this is done, ion implantation is used to create the sources and drains. The best description I can give of ion implantation is taking an ion and accelerating it to high speeds to embed itself into the targeted area, which dopes the substrate. Once this is done, a layer of nitride is added to prevent further oxide growth, which is then etched again.

Manufacturing: Back End of Line and Back End of Chip

Yet we’re still not done with how the chip is made. We just finished going over what happens in front-end-of-line (FEOL) processing. Now it’s time to go over what happens at back-end-of-line (BEOL) processing. Once the nitride layer is finished, a layer of metal is deposited over the entire system. This layer is then etched again to finish the transistor fabrication process. The result is that all the correct components for source, drain, gate, and body are implanted with metal connectors for input and output for our hypothetical CMOS inverter.

In a real chip, as many as 12 layers are added in this process, which means repeating the metal deposition step 12 times. This step is where all of the transistors are wired together, along with interlayer connections (vias), capacitors (in DRAM), dielectric isolation, and chip to package connectors. Once BEOL processing is complete, the chip is packaged and ready to be used.

CMOS Chip Structure / Cepheiden / CC BY SA

Of course, this entire production process isn’t perfect. Along the way, the wafer is tested multiple times to ensure that there are no defects from a previous step. If there are too many defects on a wafer, the entire wafer must be thrown away to avoid wasting time and money on further processing. After the FEOL processing is complete, the chip is tested and binned using a wafer prober. After the entire chip is packaged, the chip is tested again to ensure that the entire package is fully functional. The packaging and final testing stages are also known as the back end of chip fabrication.

Recap

To review everything we’ve just gone over, we started with the physics of semiconductors. Then we moved on to the physics of transistors. After that, we went over how to make logic with these transistors. Finally, we went over how to actually make transistors with logic. This would be a good place to stop, but complacency is a terrible reason to do so.

The question now is how to make things faster with less power. To do this, we have to figure out how to make the feature size smaller, in order to pack more transistors closer together. To put things in perspective, 43 years ago in 1971 with the Intel 4004 we had a feature size of 10,000 nanometers. That’s around 455 times as large as the 22nm feature size of what we see in Intel’s Haswell CPUs. Now it’s time to find out how this was achieved.

Transistors and CMOS Logic Shrinking Feature Size: Light Sources to OPC
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  • dragonsqrrl - Thursday, October 09, 2014 - link

    Article like non other, thanks. Reply
  • tarlinian - Thursday, October 09, 2014 - link

    The description of the wafer processing is pretty much completely wrong. FEOL line processing involves almost no direct oxide etches. It also completely skips shallow trench isolation and all the CMP steps involved in patterning. The wiring of the chip has no metal etch anymore either. Every metal layer in a modern (<10 years old) logic chip is produced via damascene patterning of copper. (You etch a dielectric, fill the trenches with copper and then polish the copper back.) Reply
  • JoshHo - Thursday, October 09, 2014 - link

    Much of the article is definitely quite simplified but the intent is to give a general idea of the process. I'd love to learn about this subject in more depth though. Reply
  • revoltracers - Thursday, October 09, 2014 - link

    I am printing this one out. Reply
  • tuxRoller - Thursday, October 09, 2014 - link

    Could you expand on "the holes in the p-type and the electrons in n-type are all pushed towards the junction, which causes the depletion zone to shrink" a bit?
    Connecting the + terminal @ the p semiconductor means you'll get electrons flowing into the n semiconductor. This should result in the n semiconductor being even more relatively negative, and the opposite on the p semiconductor.
    If that's the case, why wouldn't that cause a larger delta V at the junction?
    Reply
  • JoshHo - Friday, October 10, 2014 - link

    The issue here is that there is a diffusion of charge carriers. The negative end provides the potential that pushes electrons towards the depletion layer on the n-side, which has holes due to the diffusion that was previously discussed. The positive end pushes holes towards the center on the p-side, which has electrons in the depletion region. Reply
  • tuxRoller - Friday, October 10, 2014 - link

    Damn.
    IOW, I got my field directions mixed.
    Thanks.
    Reply
  • dyc4ha - Thursday, October 09, 2014 - link

    Thanks! I am still trying to digest this article, but nevertheless I know I am enjoying it! Keep it going Reply
  • PacificToast - Thursday, October 09, 2014 - link

    Nice piece. It's great to see easily accessible high-level articles being written on micro-nano IC tech. I work for a large foundry, and its often hard to explain to people what's happening inside their devices. Reply
  • Dr.Neale - Friday, October 10, 2014 - link

    First, a minor typo appears in the High-k / Metal Gate section, 3rd paragraph, 1st sentence: "comlexity" should be "complexity". (Amazing that in an article of this complexity I could only find one typo!)

    Second, I noticed that there was no mention of compound semiconductors like GaAs. I was under the impression that while many technical issues have been resolved, it remains prohibitively more expensive than silicon. Is this indeed the case, or are other factors more of an issue than cost?

    Great article, by the way, especially in regard to FinFET transistors. Makes things much clearer in my mind.

    Thanks, Josh.
    Reply

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