An Introduction to Semiconductor Physics, Technology, and Industry
by Joshua Ho on October 9, 2014 3:00 PM EST- Posted in
- Semiconductors
- CMOS
- Physics
- Industry
- Technology
Improving Transistor Performance
While it's impossible to predict what the future will hold, it's relatively easy to see what trends will take place in the near future to keep Moore's law alive. For example, instead of using dual or tri gate technologies (FinFET), it's reasonable to expect that gate-all-around (GAA) will become the next step in the evolution of transistor shapes. However, it's currently not clear when this would reach mass production, if ever.
Currently, experimental GAAFETs have only existed for around eight years. For reference, FinFETs were first made in 1999. It took around a decade and a half for any such 3D transistor to reach mass production. By continuing to scale to higher k dielectrics for the gate, lower k dielectrics between interconnects, lower resistance metals for interconnects, and even better strain engineering, we will continue to see the scaling of CMOS technology.
CNFET / Joerg Appenzeller
Unfortunately, all of these can only go so far. Fundamentally, there will be a point where silicon-based transistors cannot scale any further. Gate oxides, channel lengths, and other critical dimensions can only shrink so much before either resistance is too high or a myriad of other effects render smaller sizes infeasible.
The next step is almost impossible to predict. Perhaps graphene will take the place of silicon, but graphene currently is impossible to mass-produce and is a semi-metal, which means that it inherently lacks a band gap, although it's possible to create one. While it's been shown that semi-metal transistor logic is possible, it's currently in the very early stages and Boolean logic may be impossible with graphene. Phosphorene has promise as a semiconductor replacement for silicon, but it's similarly impossible to mass produce. Phosphorene-based FETs are still in the exploratory stages, with no actual transistor created yet.
TFET Lateral Structure / Jteherani / CC BY SA
Outside of material changes, the working mechanism of the transistor itself may change. One promising candidate right now is the tunnel field effect transistor, which relies on band to band tunneling rather than the traditional inversion layer generation for current flow. This is similar to leakage that occurs from halo doping, which results from the conduction band of the channel material aligning with the valence band of the source or drain material. As seen by the photo above, this type of transistor has an undoped body and the source/drain are of opposing types. The gate structure is unchanged from previous MOSFETs. In practice, such a transistor structure has a much higher rate of current increase per unit of voltage.
Final Words
It's been a long road, but let's quickly go over the topics covered in this article. We started with a description of semiconductor physics, then moved to the basics of MOSFETs and CMOS. Once we understood how MOSFETs work in CMOS to create logic, we moved on to the actual fabrication process of these transistors in a chip.
After all of this, we discussed how companies have increased the resolution of the fabrication process to make ever smaller transistors, and we continued by looking at how companies have increased transistor performance despite significant engineering challenges. Then we briefly covered what the future may hold for improving device performance and continuing to improve the lithography process to continue making smaller transistors.
But there is far more to be done, as literally everything we write about at AnandTech depends upon ever faster, smaller, and more efficient transistors packed as tightly as possible. Without this continued innovation, the PC, smartphone, and wearables that we see today would be impossible to make. However, continuing the scaling that we have seen within the past decades will require more ingenuity and resources than ever before to continue pushing the limits of what's possible.
Normally, we would end things here, but this time I'd like to end by thanking everyone that has helped make this article possible. It has taken weeks of research and asking questions to get to this point, and I'm sure that without help it would have taken months. Out of the many that have helped, I'd like to specifically thank Chenming Hu, a professor in the graduate school at UC Berkeley and the lead researcher in FinFET and UTB-SOI/FD-SOI, for taking the time to help clarify the reasons for SOI and FinFET. I'd also like to thank Gerd Grau, a doctoral candidate in the graduate school at UC Berkeley, and Intel's TMG for answering all kinds of questions about solid state physics in general.
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danjw - Thursday, October 9, 2014 - link
I am wondering if we haven't already hit the limits of current technology. TSMC doesn't seem to be able to produce anything more powerful than a SOC for phones and tablets on their 20nm process. While Intel seems to think they will have 14nm desktop and notebook parts out in the second quarter of next year, I wonder if they really will. Right now all we have seen from them at 14nm is similar to what TSMC is able to do at 20nm.This really concerns me as far as technology stagnating until the next big thing comes along.
Homeles - Thursday, October 9, 2014 - link
There's no end in sight. About a year ago, perhaps a little earlier, the 7 or 5nm nodes were seen as the end of Moore's Law. Advancements have been made since then, though, and scaling past the 5nm node is very likely. 10nm's "recipe" is basically all finished at Intel at this point, with "all" that's left to do at this point being increasing the yields. EUV is making good progress, finally, and should be ready for insertion at Intel's 7nm node (if they skipped it for 10nm, which they likely did).14nm has been in production for quite some time now, with Broadwell first landing in tablets later this month. The chances that Broadwell won't make it to the desktop and notebook market around the middle of next year are essentially zero.
We're still also on schedule to have 450mm wafers introduced by the end of the decade, which would reduce costs by ~30%.
Even not looking at Intel, TSMC has millions of 20nm-based products on the market right now. 20nm is roughly twice as dense as its 28nm predecessor. It doesn't really make sense to be so skeptical of progress, given that the proof pudding has already been delivered.
danjw - Thursday, October 9, 2014 - link
All those 20nm products are not desktop or notebook CPUs or GPUs, which they lead AMD and Nvidia to believe they would be able to do. Intel is way behind its original estimates to get Broadwell out, and that just in table SOCs. Intel wanted badly to get Broadwell parts out for the new school year, then it was Christmas, now it is Q2 of 2015. Yes, I think there is plenty of reason to be skeptical.EMM81 - Monday, October 13, 2014 - link
Your facts are all incorrect...If you can produce an SOC you already have all of the capability to produce GPU's or CPU's since it has logic, SRAM and graphics components already. Broadwell parts are already in the hands of vendors NOW and are being sold this year and they are not SOC's they are low power full core chips. 14nm Broadwell chips are in no way equivalent to 20nm TSMC chips. A fab can use the additional capability of a new node in different ways. They can reduce density to make chips cheaper to make, increase performance, decrease power and all of these things will be done in different ratios depending on the product. You need to work on detailed reasoning and apples to apples comparisons.errorr - Thursday, October 9, 2014 - link
The problem is that the only real advancements are more expensive per transistor and I doubt they will change.The great thing about process shrinks is that it reduces the cost per transistor.
Also I doubt EUV will ever work. It has been almost ready and a couple years away for a decade. Tell me when you don't need MW levels of power to get usable light to a wafer and maybe I will consider it.
450mm wafers have also been just a couple years away for at least 15 years. I'll believe the 2020 hype when I actually see it.
The way to the next node is easy and everyone knows they can use triple patterning. Nobody wants that because of the expense is huge already and every single circuit would have to be redrawn due to limitations on the pokygons.
I don't know what's next but the only people expecting EUV to pan out are the people who have spent billions trying to make it work and failing.
ShieTar - Friday, October 10, 2014 - link
EUV is not "almost ready", it has been commercially available for 2 years now.http://www.zeiss.com/semiconductor-manufacturing-t...
Khenglish - Thursday, October 9, 2014 - link
The problem with smaller processes is not physically producing them. The problem is that they start getting slower than larger processes. This is due to 2 reasons.1. Narrower, more resistive interconnects.
2. Increase in channel doping levels due to not having enough dopant atoms to form a P-N junction as processes increase.
1. As process sizes shrink, so do interconnects. Resistance is dependent on cross sectional area and length of the wire. As you shrink a process, the cross sectional area drops at a squared rate, while length drops at a linear rate. The end result is that wires become linearly more resistive as the process shrinks. Keeping wire length down due to resistance is also a big reason why individual core transistor counts have not been going up significantly. The cores need to stay small to keep the wire length down. Repeaters to boost current drive ability on long wires has been around starting at around 90nm.
2. If you want a 10nm process, you probably have a gate length of 10nm. The volume of a 10nm cube is 10^-18 cm^-3. High doping levels are those above around 10^17 atoms per cm. If we take a high doping level of say 10^18 atoms per cm, then we have only one single dopant atom in the entire channel region of the transistor. This means that if you are one atom off, you lose a transistor, which is difficult not to do with over 1B transistors in a microprocessor. You can dope up to around 10^21 cm^-3, but then your electron and hole mobility are terrible. Mobility is directly proportional to how much current a transistor can push, so as mobility drops performance drops. See this link for what happens to mobility as dopant levels increase.
http://ecee.colorado.edu/~bart/book/mobility.gif
abufrejoval - Saturday, October 11, 2014 - link
From what I read the problem isn't as much phyiscal or technical feasability as economical viability: Moore's law was mostly about the ability to deliver more power at a lower price for the end consumer pushing the technology. Now the economical yields of process shrinks are diminishing to the point where further shrinks won't pay for themselves.DanNeely - Thursday, October 9, 2014 - link
If you're also interested in how simpler transistors are made; hack-a-day's hosted a video lecture from someone who was producing chips with a handful of transistors on them in her home lab a few years ago.http://hackaday.com/2010/03/10/jeri-makes-integrat...
anexanhume - Thursday, October 9, 2014 - link
Graphene isn't dead in the water. There are ways to create a bandgap, for example using bilayer graphene and introducing a gap via electric fields or doping.http://www-als.lbl.gov/index.php/contact/56-bilaye...
Then you can take advantage of its remarkable carrier mobility. Mass production remains a huge issue, and I also have concerns about its effect on living creatures and the environment. http://www.gizmag.com/graphene-bad-for-environment...