Introduction and Piledriver Overview

Brazos and Llano were both immensely successful parts for AMD. The company sold tons despite not delivering leading x86 performance. The success of these two APUs gave AMD a lot of internal confidence that it was possible to build something that didn't prioritize x86 performance but rather delivered a good balance of CPU and GPU performance.

AMD's commitment to the world was that we'd see annual updates to all of its product lines. Llano debuted last June, and today AMD gives us its successor: Trinity.

At a high level, Trinity combines 2-4 Piledriver x86 cores (1-2 Piledriver modules) with up to 384 VLIW4 Northern Islands generation Radeon cores on a single 32nm SOI die. The result is a 1.303B transistor chip (up from 1.178B in Llano) that measures 246mm^2 (compared to 228mm^2 in Llano).

Trinity Physical Comparison
  Manufacturing Process Die Size Transistor Count
AMD Llano 32nm 228mm2 1.178B
AMD Trinity 32nm 246mm2 1.303B
Intel Sandy Bridge (4C) 32nm 216mm2 1.16B
Intel Ivy Bridge (4C) 22nm 160mm2 1.4B

Without a change in manufacturing process, AMD is faced with the tough job of increasing performance without ballooning die size. Die size has only gone up by around 7%, but both CPU and GPU performance see double-digit increases over Llano. Power consumption is also improved over Llano, making Trinity a win across the board for AMD compared to its predecessor. If you liked Llano, you'll love Trinity.

The problem is what happens when you step outside of AMD's world. Llano had a difficult time competing with Sandy Bridge outside of GPU workloads. AMD's hope with Trinity is that its hardware improvements combined with more available OpenCL accelerated software will improve its standing vs. Ivy Bridge.

Piledriver: Bulldozer Tuned

While Llano featured as many as four 32nm x86 Stars cores, Trinity features up to two Piledriver modules. Given the not-so-great reception of Bulldozer late last year, we were worried about how a Bulldozer derivative would stack up in Trinity. I'm happy to say that Piledriver is a step forward from the CPU cores used in Llano, largely thanks to a bunch of clean up work from the Bulldozer foundation.

Piledriver picks up where Bulldozer left off. Its fundamental architecture remains completely unchanged, but rather improved in all areas. Piledriver is very much a second pass on the Bulldozer architecture, tidying everything up, capitalizing on low hanging fruit and significantly improving power efficiency. If you were hoping for an architectural reset with Piledriver, you will be disappointed. AMD is committed to Bulldozer and that's quite obvious if you look at Piledriver's high level block diagram:

Each Piledriver module is the same 2+1 INT/FP combination that we saw in Bulldozer. You get two integer cores, each with their own schedulers, L1 data caches, and execution units. Between the two is a shared floating point core that can handle instructions from one of two threads at a time. The single FP core shares the data caches of the dual integer cores.

Each module appears to the OS as two cores, however you don't have as many resources as you would from two traditional AMD cores. This table from our Bulldozer review highlights part of problem when looking at the front end:

Front End Comparison
  AMD Phenom II AMD FX Intel Core i7
Instruction Decode Width 3-wide 4-wide 4-wide
Single Core Peak Decode Rate 3 instructions 4 instructions 4 instructions
Dual Core Peak Decode Rate 6 instructions 4 instructions 8 instructions
Quad Core Peak Decode Rate 12 instructions 8 instructions 16 instructions
Six/Eight Core Peak Decode Rate 18 instructions (6C) 16 instructions 24 instructions (6C)

It's rare that you get anywhere near peak hardware utilization, so don't be too put off by these deltas, but it is a tradeoff that AMD made throughout Bulldozer. In general, AMD opted for better utilization of fewer resources (partially through increasing some data structures and other elements that feed execution units) vs. simply throwing more transistors at the problem. AMD also opted to reduce the ratio of integer to FP resources within the x86 portion of its architecture, clearly to support a move to the APU world where the GPU can be a provider of a significant amount of FP support. Piledriver doesn't fundamentally change any of these balances. The pipeline depth remains unchanged, as does the focus on pursuing higher frequencies.

Fundamental to Piledriver is a significant switch in the type of flip-flops used throughout the design. Flip-flops, or flops as they are commonly called, are simple pieces of logic that store some form of data or state. In a microprocessor they can be found in many places, including the start and end of a pipeline stage. Work is done prior to a flop and committed at the flop or array of flops. The output of these flops becomes the input to the next array of logic. Normally flops are hard edge elements—data is latched at the rising edge of the clock.

In very high frequency designs however, there can be a considerable amount of variability or jitter in the clock. You either have to spend a lot of time ensuring that your design can account for this jitter, or you can incorporate logic that's more tolerant of jitter. The former requires more effort, while the latter burns more power. Bulldozer opted for the latter.

In order to get Bulldozer to market as quickly as possible, after far too many delays, AMD opted to use soft edge flops quite often in the design. Soft edge flops are the opposite of their harder counterparts; they are designed to allow the clock signal to spill over the clock edge while still functioning. Piledriver on the other hand was the result of a systematic effort to swap in smaller, hard edge flops where there was timing margin in the design. The result is a tangible reduction in power consumption. Across the board there's a 10% reduction in dynamic power consumption compared to Bulldozer, and some workloads are apparently even pushing a 20% reduction in active power. Given Piledriver's role in Trinity, as a mostly mobile-focused product, this power reduction was well worth the effort.

At the front end, AMD put in additional work to improve IPC. The schedulers are now more aggressive about freeing up tokens. Similar to the soft vs. hard flip flop debate, it's always easier to be conservative when you retire an instruction from a queue. It eases verification as you don't have to be as concerned about conditions where you might accidentally overwrite an instruction too early. With the major effort of getting a brand new architecture off of the ground behind them, Piledriver's engineers could focus on greater refinement in the schedulers. The structures didn't get any bigger; AMD just now makes better use of them.

The execution units are also a bit beefier in Piledriver, but not by much. AMD claims significant improvements in floating point and integer divides, calls and returns. For client workloads these gains show minimal (sub 1%) improvements.

Prefetching and branch prediction are both significantly improved with Piledriver. Bulldozer did a simple sequential prefetch, while Piledriver can prefetch variable lengths of data and across page boundaries in the L1 (mainly a server workload benefit). In Bulldozer, if prefetched data wasn't used (incorrectly prefetched) it would clog up the cache as it would come in as the most recently accessed data. However if prefetched data isn't immediately used, it's likely it will never be used. Piledriver now immediately tags unused prefetched data as least-recently-used, allowing the cache controller to quickly evict it if the prefetch was incorrect.

Another change is that Piledriver includes a perceptron branch predictor that supplements the primary branch predictor in Bulldozer. The perceptron algorithm is a history based predictor that's better suited for predicting certain branches. It works in parallel with the old predictor and simply tags branches that it is known to be good at predicting. If the old predictor and the perceptron predictor disagree on a tagged branch, the perceptron's path is taken. Improving branch prediction accuracy is a challenge, but it's necessary in highly pipelined designs. These sorts of secondary predictors are a must as there's no one-size-fits-all when it comes to branch prediction.

Finally, Piledriver also adds new instructions to better align its ISA with Haswell: FMA3 and F16C.

Improved Turbo, Beefy Interconnects and the Trinity GPU
Comments Locked

271 Comments

View All Comments

  • Kaggy - Tuesday, May 15, 2012 - link

    And at lower power consumption.
  • Pantsu - Tuesday, May 15, 2012 - link

    Unfortunately for AMD, the processor is only a small part of the laptop BOM. Even if Trinity is cheaper, the difference in the end product is not that big. Still, the mainstream 15" cheapo laptop is perhaps the last refuge AMD has.

    Looks like Trinity is still the way to go for low end gaming, but it's disconcerting to see HD4000 actually beat it in few tests. AMD really needs to get a better CPU architecture going.

    HSA is still long ways to go too, and I just don't see AMD pulling off the necessary developer support for it to really work, unless Intel goes along the same lines, in which case they might as well just give up.
  • iwod - Tuesday, May 15, 2012 - link

    I am guessing Haswell will have some CPU improvement with FMA, New AVX, etc... and 3 times faster Graphics..... I dont see Trinity or what ever behind it having too much hope.

    I am also wondering if Intel could further improve those games performance with better drivers. Again Intel may have caught up with the hardware department ( The easier part ), their drivers are still lacking behind.
  • Spunjji - Tuesday, May 15, 2012 - link

    I'd like to think that an AMD CPU with their current GCN graphics on a 28nm-or-smaller process would at least be GPU competitive with Intel. We live in interesting, times, though.
  • duploxxx - Tuesday, May 15, 2012 - link

    you can always believe marketing that they will be able to perform that kind of GPU leap while in the past they have always struggled to enhance. Sure the 4000 is already getting better (near Liano perf) it only shines in the few synthetical benchmarks and where the AMD is limited to CPU performance.

    perhaps try a few higher res games and see how much is left from the Intel GPU...

    AMD is limited to memory bandwidth, Intel will suffer from the same.
  • cyrusfox - Tuesday, May 15, 2012 - link

    So when will I be able to find a good trinity laptop with backlit keyboard in a small 13" form factor or preferably smaller. I would like to upgrade from brazos, and brazos 2.0 isn't going to hack it.
  • JarredWalton - Tuesday, May 15, 2012 - link

    This is the hard part: just about every OEM that makes an AMD laptop ends up targeting the budget market, and in that market they cut every corner possible. Forget quality LCDs (which would add around $10 to the BoM for most laptops), forget better build materials, and forget amenities like backlit keyboards. Oh, I'm sure someone will make a Trinity laptop with a backlit keyboard, but then they'll probably ask $800 for it. HP has their Envy 14 coming in "Sleekbook" trim that might get you a backlit keyboard, though--and it's price starts at $700.
  • FrontBoard - Tuesday, May 15, 2012 - link

    Trinity is the name of a river in Texas, just as Comal and Brazos are. That is likely where the codenames come from.
  • kevith - Tuesday, May 15, 2012 - link

    Thanks!
  • JarredWalton - Tuesday, May 15, 2012 - link

    For the record, I *did* know that AMD is grabbing names of rivers. I guess it could be better stated: "I wonder if AMD was trying to have a secondary meaning with their codename." And it was a nice hook for the conclusion. :-)

Log in

Don't have an account? Sign up now