Intel has already disclosed that it will have a next generation Atom core, code named Tremont, which is to appear in products such as the Foveros-based hybrid Lakefield, as well as Snow Ridge designed for 5G deployments. In advance of the launch of the core and the product, it is customary for some documentation and tools to be updated to prepare for it; in this case, one of those updates has disclosed that the Tremont core would contain an L3 cache – a first for one of Intel’s Atom designs.

01.org is an Intel website which hosts all of its open source projects. One of those projects is perfmon, a simple performance monitoring tool that can be used by developers to direct where code may be bottlenecked by either throughput, memory latency, memory bandwidth, TLBs, port allocation, or cache hits/misses. In this case, the profiles for Snow Ridge have been uploaded to the platform, and one of the counters provided includes provisions for L3 cache monitoring. This provision is directly listed under the Tremont heading.

Enabling an L3 cache on Atom does two potential things to Intel’s design: it adds power, but also adds performance. By having an L3, it means that data in the L3 is quicker to access than it would be in memory, however there is an idle power hit by having L3 present. Intel can mitigate this by enabling parts of the L3 to be powered on as needed, but there is always a tradeoff. There can also be a hit to die area, so it will be interesting to see how Intel has changed the microarchitecture of it’s Atom design. There is also no indication if the Tremont L3 cache is an inclusive cache, or a non-inclusive cache, or if it can be pre-fetched into, or if it is shared between cores or done on a per-core basis.

Intel’s Atom roadmap, as disclosed last year at Architecture day, shows that the company is planning several more generations of Atom core, although beyond Tremont we get Gracemont in 2021, and beyond that is ‘increased ST Perf, Frequency, Features’ listed around 2023. In that time, Intel expects to launch Sunny Cove, Willow Cove, and Golden Cove on the Core side.


Lakefield

The first public device with Tremont inside is expected to be the Core/Atom hybrid Lakefield processor, which uses Intel’s new Foveros stacking technology. We know that this design will have one Sunny Cove core and pair it with four Tremont cores. Intel expects chip production of Lakefield for consumer use by the end of the year.

Related Reading

Source: InstLatX64, 01.org

POST A COMMENT

63 Comments

View All Comments

  • mode_13h - Monday, July 15, 2019 - link

    Uh, shrinkwrapped? You mean shrunken? Reply
  • GreenReaper - Tuesday, July 16, 2019 - link

    Intel found a way to one-up its original replacement of solder with thermal pads. Reply
  • HStewart - Monday, July 15, 2019 - link

    Tremont is not based off Skylake but closer to Sunny Core which is entirely new architexture. I yet discover accurate performance measure between x86 and ARM. Plus this is a completely new architexture and it would be hard to compare to current cpu designs and especially existing atom's. Reply
  • IntelUser2000 - Tuesday, July 16, 2019 - link

    Tremont is not Sunny Cove based!

    Tremont is its own development that builds upon Goldmont Plus. And we don't know any details. Certainly not enough to claim it looks like anything.
    Reply
  • III-V - Monday, July 15, 2019 - link

    I don't recall people ever dissing big/little. I just remember people thinking it would be a pain in the ass to implement.

    I also recall you coming up with a lot of "alternative histories and alternative truths" back then too. Seems you haven't changed.
    Reply
  • R0H1T - Tuesday, July 16, 2019 - link

    >I also recall you coming up with a lot of "alternative histories and alternative truths" back then too.

    Like what ~ Intel would be benevolent if AMD disappeared, lower their prices even because ARM? Wait that was the IDF.

    >I don't recall people ever dissing big/little.

    It's still there, you can go search yourself. "More cores" gimmick & all that.
    Reply
  • name99 - Monday, July 15, 2019 - link

    big.LITTLE is not just yet cores, it was a very specific IMPLEMENTATION of that idea. And it wasn’t a great implementation. Which is why even ARM has ditched it, replaced with DynamIQ...

    You’ll get more out of tech sites if you distinguish
    - the commenters who know what they are talking about from the idiots
    - exactly WHAT is being criticized when (knowledgeable) commenters criticize something. Knowledgeable criticism usually accepts some aspect of an idea is valuable, while also pointing out other parts that are problematic.
    Reply
  • Jorgp2 - Monday, July 15, 2019 - link

    I feel like low power cores are more exciting in general, since you have to balance performance with power. Reply
  • mode_13h - Monday, July 15, 2019 - link

    No, please leave the cats dead and buried!

    If Intel adds AVX to their atom cores (as the slides suggest they will), I wonder how much area advantage they'll still hold over Zen. If it's only like a factor of 2, then I'd rather have one Zen2 cores with HT than 2 Atom-derived cores.
    Reply
  • IntelUser2000 - Tuesday, July 16, 2019 - link

    Big.Little like setups have existed as an idea for future compute in academia for a long time.

    It was actually the former head of Intel Labs, Justin Rattner, that showed the idea to the public back in 2005. It was called "Platform 2015".

    Had 10nm not been so ambitious(they go as far as admit this in their recent presentation) we might have really seen such setups in 2015-2016.
    Reply

Log in

Don't have an account? Sign up now