Ice Lake 10nm Xeon Scalable On Display

One of the more sedate talks at the event was discussing Intel’s approach in the datacenter. We’ve covered this story in detail, especially at Intel’s Data-Centric Summit only a few months ago. Intel has stated that Cascade Lake and Cooper Lake are the next two products for the enterprise market, both built on 14nm, focusing on enhanced security as well as AI instructions to help with acceleration. We also know that after these two Intel will have Ice Lake Scalable built on 10nm, but that’s about it.

To be honest, we don’t actually know much more than what we did back then. Intel confirmed that Ice Lake will be built using Sunny Cove cores. But Intel also showed off what they said was an Ice Lake Xeon 10nm processor and package, as shown in the image above.

Color me skeptical, but what was held up is likely either not ICL-SP or just silicon that doesn’t work. In order to make those products, Intel would have to have pumped out at least one large (350mm2+?) die that worked and then put it into a package with a heatspreader. Intel finally seems to be happy discussing a few products on 10nm, as shown at this event, but all the 10nm hardware is based on tiny 100mm2 or smaller silicon. Given Intel’s documented problems, I would have loved that CPU that was held up in the air to be Ice Lake-SP. But I’ll need to see something more concrete to believe it at this point; it’s too much of a jump.

Ending Intel’s Architecture Day

As I’m writing this, it is 3am PT and only a couple of hours away from Intel’s listed embargo time. The event finished 10 hours ago (a few of us skipped the end event drinks to get to writing) and despite the short time to write it all up, it was a good event overall. For the first time in a good while, Intel decided to talk shop, and in an honest way with very little hand waving. One could argue that in every discussion point, Intel raised more questions than they answered, but the positive here is that questions are being answered, and Intel is willing to share things like roadmaps into 2021, demonstrations of some exciting new products for 2019/2020, and a taste of how they are progressing in both manufacturing and microarchitecture. Hopefully Intel will feel the same and this can become a yearly cadence. The trio of Keller, Koduri, and Murthy, is a strong team to field to the press, and this event fits that bill.

To end this piece, I’m going to put in the Q&A section from day’s presentations, as well as some of the questions put in my particular round-table. It’s an interesting read, and it helps that Jim is full of memorable quotes.

Intel’s First Fovoros and First Hybrid x86 CPU: Core plus Atom in 7 W on 10 nm Intel Made Something Really Funny: Q&A with Raja, Jim, and Murthy
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  • jjj - Wednesday, December 12, 2018 - link

    And you acted like someone clueless that has put all his savings in Intel's stock based on brad, "Large revenue stream" LOL, you don't know anything about the product, the target market, about the packaging solution but you get all wet.

    Anyway, took a look at the slides and they do actually provide some relevant details that yuo seem to not notice. They say face-face, bump pitch at 36um and bump density at 828.mm2.
    Reply
  • Spunjji - Thursday, December 13, 2018 - link

    Your comments are unnecessarily aggressive, dripping with unwarranted confidence and really unpleasant to read. Please spend more time offline. Reply
  • jjj - Wednesday, December 12, 2018 - link

    For the hell of it, I'll add this IMEC slide (different versions out there but this one was the first i could find)
    http://www.techdesignforums.com/practice/files/201...
    Reply
  • iwod - Thursday, December 13, 2018 - link

    ignore the trolls. Reply
  • Raqia - Wednesday, December 12, 2018 - link

    That's a nice fan on their fanless SoC design. It seems like Intel is really playing catch up with their ultra mobile designs (with a power envelope that's likely still above phones) fabbed on a late 10nm design and only now doing things like heterogeneous cores and PoP memory that the AX and Snapdragons have been doing for a few years now.

    I wonder what portion of that block diagram's compute reside on the P1222 (which looks bigger die space wise on their diagram than the P1274 but may pack fewer transistors.) They mentioned IO but it wouldn't make too much performance sense for caches and coherency to segregate the Big/Little cores onto separate dies, so it likely contains the ISPs and memory controllers. Where the GPU is located is another interesting question and no LTE modem can be seen on the block diagram. This is also likely to have higher packaging cost and worse integration than the AX, Kirins, PXX's or Snapdragons.
    Reply
  • A5 - Wednesday, December 12, 2018 - link

    Dev boards have fans because they don't have a chassis to sink heat into. If it's like every other dev board I've used, it is probably a 8k RPM screamer, too. Reply
  • The_Assimilator - Wednesday, December 12, 2018 - link

    Seems like you failed to read page 4: "These were development systems with these funky looking heatsinks and loud fans to ensure there was no thermal throttling." Reply
  • Raqia - Wednesday, December 12, 2018 - link

    My comment was in reference to their new Atom lineup which are supposed to be fanless, not Sunny Cove which operates in a much higher power envelope. Surely they could use a larger passive cooling unit to demonstrate what's supposed to be a key feature of that product; my other point is that Intel's aiming for something later next year that seems much less advanced than what Apple, Huawei, Mediatek, and Qualcomm already have in production today. Reply
  • The_Assimilator - Thursday, December 13, 2018 - link

    And, again, the Fovoros setup was a demo board in the open air, not a production chip inside a device designed around dissipating the heat it outputs. Reply
  • Spunjji - Thursday, December 13, 2018 - link

    If that's what you took from that part of the presentation then I feel you missed the point. What Intel are doing in terms of chip layout is something none of the companies you mentioned are able to do yet, which is the fundamental point here - whether it results in a useful product is another matter entirely, but it's still fascinating and not same-same.

    To back up the other people who responded to you, again, the fan is irrelevant. It's a dev board.
    Reply

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