Samsung this week announced that its 8LPP fabrication process, which it formally introduced earlier this year, had passed qualification tests. The manufacturing technology will be used to produce advanced SoCs next year and will be Samsung’s final leading edge process based solely on DUV lithography before the company adopts EUV for select layers with its 7LPP process node.

The 8LPP fabrication technology is an evolution of Samsung’s 10 nm node that uses narrower metal pitches and promises a 10% area reduction (at the same complexity) as well as a 10% lower power consumption (at the same frequency and complexity) compared to the 10LPP process. Samsung does not disclose which standard cell libraries are used by the 8LPP, but the 10LPP relies on 8.75T and 10.5T, so it is logical to expect the 8LPP to use similar ones. Samsung does not disclose whether the 8LPP relies on quadruple patterning techniques, or if it continues to use triple patterning like the company’s 10LPE/10LPP processes, but QPT is an option to shrink die sizes at the increase in cost (and potential defects).

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  14LPP
vs 28LPP
10LPE
vs 14LPE
10LPE
vs 14LPP
10LPP
vs 10LPE
10LPU
vs
10LPE
8LPP
vs 10LPP
Power 60% 40% 30% ~15% ? 10%
Performance 40% 27% >10% ~10% ? ?
Area Reduction 50% 30% 30% none ? 10%

Samsung plans to use the 8LPP manufacturing technology to produce SoCs for various applications, including smartphones, cryptocurrency and networks/servers, but does not elaborate on exact designs or clients. The only thing we do know is that Qualcomm will be one of the first customers to adopt the 8LPP and that the company expects the new technology to ramp up fast (which possibly means that it uses the same libraries and manufacturing equipment as the 10 nm nodes).

“8LPP will have a fast ramp since it uses proven 10 nm process technology while providing better performance and scalability than current 10nm-based products said RK Chunduru, a senior vice president of Qualcomm.

Neither Samsung nor Qualcomm are disclosing when they expect to ship their first 8LPP chips, but since the technology has passed qualification tests (meaning that quality and reliability of ICs made using the technology meet certain guidelines, such as those proposed by JEDEC), we would expect the SoCs to arrive in the coming quarters.

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Source: Samsung

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  • HStewart - Thursday, October 19, 2017 - link

    "TSMC and Samsung 7nm are also better than Intel 10nm"

    Personally I think this naming of 10nm vs 7nm process today reminds me the frequency wars in the past but in opposite direction. I believe the real thing is how many transistors can be pack in same area. From specs what I hear about what is coming in Cannon Lake and such and other slide I seen on Intel's process - I think we probably find that Intel's process is totally going to surprise people especially Samsung and TSMC.

    But truthfully, it any ones guess until Intel releases - the news today about Icy Lake look very promising - especially in technical specs. I really love the faster REP MOV - if done right ( backward application compatible ) this could be a serious game change - I done almost 7 years straight of assembly programming on OS level and this makes a huge difference.
    Reply
  • Santoval - Thursday, October 19, 2017 - link

    Yes, Intel has managed to pack 102 million transistors per mm^2 (at "10nm") for Cannon Lake and Ice Lake. If I recall correctly TSMC and Samsung's "10nm" must be at around 45 to 55 million transistors per mm^2 (an estimate, since they do not report transistor densities). Better than Intel's "14nm" but way less dense than Intel's "10nm". Intel took a bigger leap in transistor density at "10nm", so the others will find it very hard to even match at it their "7nm". I doubt they will be able to go beyond 90 million transistors per mm^2, maybe 95 million tops. Which is why they avoid reporting transistor densities. Reply
  • Wilco1 - Thursday, October 19, 2017 - link

    We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm. So even if Intel 14nm is denser in theory, that doesn't turn out to be the case in actual chips.

    For the next generation of processes, TSMC 7nm has 117 million transistors per mm^2, Samsung 127, so their theoretical density is better than Intel 10nm at 103 million. Actual chips would likely show a far larger density advantage like on 14nm.
    Reply
  • HStewart - Thursday, October 19, 2017 - link

    These are not the numbers I heard - I heard under 100 for either Samsung or TSMC

    "We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm"

    You lost all credit with this statement - possibly Apple - but no way AMD. From everything I seen from AMD they must double up or quad up CPU cores in a die to make it there. Also for AVX-256 they use double on 128 bit vectors

    By the way Ice Lake is likely be much denser than Canon Lake.
    Reply
  • Wilco1 - Friday, October 20, 2017 - link

    Seriously why are you denying reality? There have been multiple articles comparing density, including recently on here about AMD vs Intel SRAM density. There was even a marketing response by Intel trying to explain away why Apple chips had higher transistor density.

    > By the way Ice Lake is likely be much denser than Canon Lake.

    That's simply your wish. In reality the 14+/++ process are significantly less dense than 14nm since the CPP has been relaxed to 84nm - that's a loss of 20% in density right there.
    Reply
  • melgross - Friday, October 20, 2017 - link

    We know that? Can you site some credible source for that? Reply
  • HStewart - Thursday, October 19, 2017 - link

    Exactly they will never reported transistor density. Because it they can use nm rating to say in theory they are twice as dense as 14nm. Ice Lake is a 10nm+ and is suppose to have significant improvements over Cannon Lake.

    I am actually a little confused about the latest article about Cannon Lake - I heard it only going to be for Ultra Mobile laptops and tablets. But some information like AVX512 means that this chips is going to be extremely denser then current processors. Just a guess.

    BTW I serious doubt if the 10nm version from TSMC and Samsung are 45 to 55 million, I serious doubt 7nm will even be 90 to 95, more likely would be 70 million.
    Reply
  • Wilco1 - Friday, October 20, 2017 - link

    Apple A11 has 48 million transistors per mm^2 (4.3B in 89 mm^2). What is there to doubt?

    Note TSMC 7nm transistor density improves not just by CPP and MMP scaling but gets an extra 25% via track scaling as well.
    Reply
  • psychobriggsy - Tuesday, October 24, 2017 - link

    Estimates put TSMC 7nm at 116 mT/mm^2, SS 7nm at 127 mT/mm^2.

    I can understand not wanting to report transistor densities when your competitor who suddenly wants to use them has cherrypicked the reporting methodology.

    Doesn't matter anyway, firstly availability matters: both TSMCs and SS's 10nm are working, mass production processes, and Intel's ... well, where is it? And secondly, it's what you do with it that counts.
    Reply
  • Wilco1 - Thursday, October 19, 2017 - link

    This has realistic estimates for transistor density for Intel 10nm vs TSMC/Samsung 7nm based on published details: https://www.semiwiki.com/forum/content/6713-14nm-1... - nothing surprising.

    REP MOV has been a ridiculously slow instruction since the early days of x86, and it still has a huge penalty on the latest implementations. GLIBC contains the fastest memcpy implementations - none of them uses REP MOV, so that says it all. Even if the penalty is smaller, REP MOV is never going to be fast.
    Reply

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