Memory Subsystem: Bandwidth

Measuring the full bandwidth potential with John McCalpin's Stream bandwidth benchmark is getting increasingly difficult on the latest CPUs, as core and memory channel counts have continued to grow.  We compiled the stream 5.10 source code with the Intel compiler (icc) for linux version 17, or GCC 5.4, both 64-bit. The following compiler switches were used on icc:

icc -fast  -qopenmp  -parallel (-AVX) -DSTREAM_ARRAY_SIZE=800000000 

Notice that we had to increase the array significantly, to a data size of around 6 GB. We compiled one version with AVX and one without. 

The results are expressed in gigabytes per second.

Meanwhile the following compiler switches were used on gcc:

-Ofast -fopenmp -static -DSTREAM_ARRAY_SIZE=800000000

Notice that the DDR4 DRAM in the EPYC system ran at 2400 GT/s (8 channels), while the Intel system ran its DRAM at 2666 GT/s (6 channels). So the dual socket AMD system should theoretically get 307 GB per second (2.4 GT/s* 8 bytes per channel x 8 channels x 2 sockets). The Intel system has access to 256 GB per second (2.66 GT/s* 8 bytes per channel x 6 channels x 2 sockets).

Stream Triad (6 GB)

AMD told me they do not fully trust the results from the binaries compiled with ICC (and who can blame them?). Their own fully customized stream binary achieved 250 GB/s. Intel claims 199 GB/s for an AVX-512 optimized binary (Xeon E5-2699 v4: 128 GB/s with DDR-2400). Those kind of bandwidth numbers are only available to specially tuned AVX HPC binaries. 

Our numbers are much more realistic, and show that given enough threads, the 8 channels of DDR4 give the AMD EPYC server a 25% to 45% bandwidth advantage. This is less relevant in most server applications, but a nice bonus in many sparse matrix HPC applications. 

Maximum bandwidth is one thing, but that bandwidth must be available as soon as possible. To better understand the memory subsystem, we pinned the stream threads to different cores with numactl. 

Pinned Memory Bandwidth (in MB/sec)
Mem
Hierarchy
AMD "Naples"
EPYC 7601
DDR4-2400
Intel "Skylake-SP"
Xeon 8176
DDR4-2666
Intel "Broadwell-EP"
Xeon E5-2699v4
DDR4-2400
1 Thread 27490 12224 18555
2 Threads, same core
same socket
27663 14313 19043
2 Threads, different cores
same socket
29836 24462 37279
2 Threads, different socket 54997 24387 37333
4 threads on the first 4 cores
same socket
29201 47986 53983
8 threads on the first 8 cores
same socket
32703 77884 61450
8 threads on different dies 
(core 0,4,8,12...)
same socket
98747 77880 61504

The new Skylake-SP offers mediocre bandwidth to a single thread: only 12 GB/s is available despite the use of fast DDR-4 2666. The Broadwell-EP delivers 50% more bandwidth with slower DDR4-2400. It is clear that Skylake-SP needs more threads to get the most of its available memory bandwidth.

Meanwhile a single thread on a Naples core can get 27,5 GB/s if necessary. This is very promissing, as this means that a single-threaded phase in an HPC application will get abundant bandwidth and run as fast as possible. But the total bandwidth that one whole quad core CCX can command is only 30 GB/s.

Overall, memory bandwidth on Intel's Skylake-SP Xeon behaves more linearly than on AMD's EPYC. All off the Xeon's cores have access to all the memory channels, so bandwidth more directly increases with the number of threads. 

Testing Notes & Benchmark Configuration Memory Subsystem: Latency
POST A COMMENT

217 Comments

View All Comments

  • coder543 - Tuesday, July 11, 2017 - link

    Right, of course. Ryzen is a copy-and-paste of Haswell.

    Don't make me laugh.
    Reply
  • psychobriggsy - Tuesday, July 11, 2017 - link

    Indeed it is a ridiculous comment, and puts the earlier crying about the older Ubuntu and GCC into context - just an Intel Fanboy.

    In fact Intel's core architecture is older, and GCC has been tweaked a lot for it over the years - a slightly old GCC might not get the best out of Skylake, but it will get a lot. Zen is a new core, and GCC has only recently got optimisations for it.
    Reply
  • EasyListening - Wednesday, July 12, 2017 - link

    I thought he was joking, but I didn't find it funny. So dumb.... makes me sad. Reply
  • blublub - Tuesday, July 11, 2017 - link

    I kinda miss Infinity Fabric on my Haswell CPU and it seems to only have on die - so why is that missing on Haswell wehen Ryzen is an exact copy? Reply
  • blublub - Tuesday, July 11, 2017 - link

    Your actually sound similar to JuanRGA at SA Reply
  • Kevin G - Wednesday, July 12, 2017 - link

    @CajunArson The cache hierarchy is radically different between these designs as well as the port arrangement for dispatch. Scheduling on Ryzen is split between execution resources where as Intel favors a unified approach. Reply
  • bill.rookard - Tuesday, July 11, 2017 - link

    Well, that is something that could be figured out if they (anandtech) had more time with the servers. Remember, they only had a week with the AMD system, and much like many of the games and such, optimizing is a matter of run test, measure, examine results, tweak settings, rinse and repeat. Considering one of the tests took 4 hours to run, having only a week to do this testing means much of the optimization is probably left out.

    They went with a 'generic' set of relative optimizations in the interest of time, and these are the (very interesting) results.
    Reply
  • CoachAub - Wednesday, July 12, 2017 - link

    Benchmarks just need to be run on as level as a field as possible. Intel has controlled the market so long, software leans their way. Who was optimizing for Opteron chips in 2016-17? ;) Reply
  • theeldest - Tuesday, July 11, 2017 - link

    The compiler used isn't meant to be the the most optimized, but instead it's trying to be representative of actual customer workloads.

    Most customer applications in normal datacenters (not google, aws, azure, etc) are running binaries that are many years behind on optimizations.

    So, yes, they can get better performance. But using those optimizations is not representative of the market they're trying to show numbers for.
    Reply
  • CajunArson - Tuesday, July 11, 2017 - link

    That might make a tiny bit of sense if most of the benchmarks run were real-world workloads and not C-Ray or POV-Ray.

    The most real-world benchmark in the whole setup was the database benchmark.
    Reply

Log in

Don't have an account? Sign up now