Today in collaboration with TSMC, ARM's physical IP division is announcing the tapeout of a 10nm test chip demonstrating the company's readiness for the new manufacturing process. The new test chip is particularly interesting as it contains ARM's yet-to-be-announced "Artemis" CPU core. ARM discloses that tapeout actually took place back in December 2015 and is expecting silicon to come back from the foundry in the following weeks. 

The test chip serves as a learning platform for both ARM and TSMC in tuning their tools and manufacturing process to achieve the best results in terms of performance, power, and area. ARM actually implemented a full 4-core Artemis cluster on the test chip which should serve as a representative implementation of what vendors are expected to use in their production designs. The test chip also harbours a current generation Mali GPU implementation with 1 shader core that serves as a demonstration of what vendors should expect when choosing ARM's POP IP in conjunction with its GPU IP. Besides the CPU and GPU we find also a range of other IP blocks and I/O interfaces that are used for validation of the new manufacturing process.

TSMC's 10FF manufacturing process primarily promises a large improvement in density with scalings of up to 2.1x compared to the previous 16nm manufacturing node. At the same time, the new process is able to achive 11-12% higher performance at each process' respective nominal voltage, or a 30% reduction in power at the same frequency.

In terms of a direct comparison between a current Cortex A72 design on 16FF+ and an Artemis core on 10FF on the preliminary test chip with an early physical design kit (PDK) we see that the new CPU and process are able to roughly halve the dynamic power consumption. Currently clock frequencies on the new design still don't reach what is achievable on the older more mature process and IP, but ARM expects this to change in the future as it continues to optimise its POP and the process stabilises.

As manufacturing processes increasingly rise in their complexity, physical design implementation becomes an increasingly important part of CPU and SoC designs. As such, tools such as ARM's POP IP become increasingly important for vendors to be able to achieve a competitive result both in terms of PPA and time-to-market of an SoC. Today's announcement serves as demonstration of ARM commitment to stay ahead of the curve in terms of enabling its partners to make the best out of the IP that they license.

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  • close - Thursday, May 19, 2016 - link

    Probably from the fact that Apple used almost exclusively 2 core implementations (with one 3 core exception) as opposed to the now common 4-8 core implementations used by others and maybe even the fact that Apple almost always leads the single threaded performance charts.

    Using a quarter of the cores to achieve similar performance and battery life suggests that they heavily optimize for single threaded operation.
    Reply
  • schneeb - Wednesday, May 25, 2016 - link

    Those cores are often big/small not an actual quad core. Reply
  • Flunk - Tuesday, May 24, 2016 - link

    I'm not an iOS expert but I was under the impression that the UI only runs on a single thread and secondary threads can only be used for background processing. Once again, I've only wrote a few iOS apps so it's possible this is out of date or incorrect. Reply
  • jjj - Wednesday, May 18, 2016 - link

    So they push clocks up with Artemis and it's likely tiny on 10nm, tending towards half a mm2. They do need a bigger core , at the very least for 7nm given that TSMC is doing a process version for the server market.
    Interesting that in the power/perf slide they mention Artemis on 16ff+. Some gains from the architectural changes, some from higher clocks, should be nice since A72 is fast as it is.
    Reply
  • JamieK - Wednesday, May 18, 2016 - link

    This is exciting that mobile and ARM are staying step by step with Intel on process improvements. I have read, often, though that the Intel and ARM gate sizes etc., mean that all 10nm chips aren't equally a 'real 10nm'.

    An in depth Anandtech comparison of the process technology comparisons at 16/10nm would be very interesting.

    A lot of it is marketing but they are genuinely new processes on smaller technology, the question is how small?

    Can anyone recommend such an article?
    Reply
  • Andrei Frumusanu - Wednesday, May 18, 2016 - link

    So far I don't think TSMC has commented on actual dimensions other than saying 10FF is 2.1x denser than 16FF. It should be a solid die shrink according to that. Reply
  • jjj - Wednesday, May 18, 2016 - link

    Anandtech can't do that comparison, they will never have access to that kind of data. A comparison is a lot more than just physical dimensions.There are design rules, there are costs ,it's a lot more complicated than just x or y nm. Smaller doesn't always mean better.
    You could look at this pdf ,page 17 and beyond but it's marketing so don't trust it too much http://files.shareholder.com/downloads/INTC/0x0x86...
    On slide 19 Intel's excuse for their lower density is that they use tall calls for a pretty large area - something that TSMC will be doing too with their 7nm HPC process version.
    The easiest comparison would be power,perf and cost for an ARM core and some SRAM for each foundry but unlikely we'll ever see that kind of data.
    Reply
  • witeken - Wednesday, May 18, 2016 - link

    Summary: http://farm9.staticflickr.com/8125/15650137820_be3... Reply
  • witeken - Wednesday, May 18, 2016 - link

    Also, 10nm of TSMC will be 0.53x the area of 16nm. Reply
  • extide - Monday, May 23, 2016 - link

    Check out this image, it illustrates the differences between many of the process sizes: http://images.teraknor.net/Cell-SizeComparison-ful... Reply

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