Speaking to partners last week as part of their annual Open Innovation Platform forum in Europe, a big portion of TSMC's roadshow was dedicated to the next generation of the company's foundry technology. TSMC's 2 nm-class N2, N2P, and N2X process technologies are set to introduce multiple innovations, including nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM) capacitor over the next few years. But in order to take advantage of these innovations, TSMC warns, chip designers will need to use all-new electronic design automation (EDA), simulation, and verification tools as well as IP. And while making such a big shift is never an easy task, TSMC is bringing some good news to chip designers early-on: even with N2 still a couple...

TSMC Shares More Info on 2nm: New MIM Capacitor and Backside PDN Detailed

TSMC has revealed some additional details about its upcoming N2 and N2P process technology at its European Technology Symposium 2023. Both production nodes are being developed with high-performance computing...

15 by Anton Shilov on 5/31/2023

TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To Roadmap

At its 2023 North American Technology Symposium today, TSMC has disclosed additional details about its plans for its forthcoming N2 2nm-class production nodes in 2025 – 2026 and beyond...

38 by Anton Shilov on 4/26/2023

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