3D Packaging

Earlier this year, new Intel CEO Pat Gelsinger outlined his new ‘IDM 2.0’ vision for Intel. This vision was a three pronged strategy based on improving its own process node technology, mixing in other foundry technology where needed, and also realigning its manufacturing for a new foundry service offering allowing other semiconductor companies to use Intel’s manufacturing expertise. As part of the journey towards Gelsinger’s IDM 2.0 vision, we were told to expect updates at a more regular cadence, and the announcement of ‘Intel Accelerated’ in a couple of weeks is the next event on the calendar.

3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap

Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB.TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect...

15 by Dr. Ian Cutress on 9/2/2020

Intel Next-Gen 10-micron Stacking: Going 3D Beyond Foveros

One of the issues facing next-generation 3D stacking of chips is how to increase the density of the die-to-die interface. More connections means better data throughput, reducing latency and...

32 by Dr. Ian Cutress on 8/14/2020

Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology

Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or “X-Cube”, allowing chip-stacking of SRAM dies on top of a base logic die through TSVs. Current...

21 by Andrei Frumusanu on 8/14/2020

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