3D Packaging

Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB.TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect to each other. At the simple level, two chips can be connected through the printed circuit board – this is cheap but doesn’t allow for great bandwidth. Above this simple implementation, there are a variety of ways to connect multiple chiplets together, and TSMC has a number of these technologies. In order to unify all the different names it gives to its variants of its 2.5D and 3D packaging, TSMC has introduced its new overriding brand: 3DFabric.

Intel Next-Gen 10-micron Stacking: Going 3D Beyond Foveros

One of the issues facing next-generation 3D stacking of chips is how to increase the density of the die-to-die interface. More connections means better data throughput, reducing latency and...

32 by Dr. Ian Cutress on 8/14/2020

Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology

Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or “X-Cube”, allowing chip-stacking of SRAM dies on top of a base logic die through TSVs. Current...

21 by Andrei Frumusanu on 8/14/2020

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