The History

The Athlon was the first non-Intel x86 processor to move from the conventional socketed design of the time (Pentium MMX, K6, K6-2, K6-III) to a slot-based interface connector, commonly known as Slot-A.  The reason behind the move to a slot-based design was to enable the Athlon to feature a fast L2 cache that would remain on the processor card itself, thus removing the bottlenecks that having the L2 cache on the motherboard caused in the earlier days of Socket-7 motherboards. 

The 0.25-micron Athlon die already took up a whopping 184 mm^2 of surface area and there was definitely no room for an on-die L2 cache, so the L2 cache remained on the processor card.  With the release of the Athlon 750, AMD presented the first modification to the Athlon core, which was the move to a 0.18-micron die fabrication process, which reduced the surface area of the newly codenamed K75 core from 184 mm^2 to 102 mm^2, or 55% of the original die size. 

The 0.18-micron manufacturing process allowed AMD to scale up to higher clock speeds, since the processor's heat and power consumption statistics were noticeably reduced; unfortunately, the fact that AMD had to rely on third party manufacturers to produce the Athlon's high speed L2 cache limited the growth potential of the Athlon.

The next step in the Athlon's progression was to take advantage of the smaller die size of the K75 core and integrate the L2 cache onto the die itself.  By placing the L2 cache on the die of the Athlon, the latency of the L2 cache can be improved since it is much easier for the CPU to access the L2 cache if its physically located on the die of the CPU rather than if its located off of the CPU on the processor card itself. 

Having the L2 cache on the die also allows it to operate at the same frequency as the rest of the die, meaning that it runs at the core clock speed of the CPU.  The main benefit of this is that it allows the CPU's performance to scale properly with clock speed since, for every increase in clock frequency, you get a similar increase in L2 cache frequency as well. 

Index The Basics

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