VIA continues to swap back and forth with NVIDIA as the premiere Athlon 64 core logic, but any and all efforts in the Pentium/Celeron arena have been largely dominated by SIS and Intel. Within the last 18 months with the inception of the PT800 chipset we have seen a strong push within the company for a contending Pentium 4 chipset. As a dual channel contender with Intels i848P chipset, VIA has done better for itself - although many can contend that VIA is only stealing competition from SiS and barely scratching business at Intel.

So where do we see VIA going in the next six months? For one, it looks like VIA wants to pick up the pieces where Intel does not; particularly with dual PCIe x16 connectors. As you may recall, Intel's high end server/workstation Tumwater chipsets support two PEG slots, even though one is merely an x8 lane with with an x16 interface. As somewhat of an unexpected, VIA looks like they will not only support, but encourage NVIDIA's SLI movement. It may be the case that VIA is working on some DeltaChrome SLI project of their own, but most likely it seems that VIA does not want to be left behind in the multi display market.

VIA's push for dual PEG interfaces will show up on both Intel and AMD platforms. The implementation of K8T890 Pro looks to be the most ambitious.

However, one thing that was skirted around in the roadmaps was the lack of PCIe lanes on K8T890 andK8T890 Pro. We will most likely see 2 x1 lanes from the southbridge, but only one x4 lane on K8T890. This x4 lane is not mentioned in K8T890 Pro roadmap, and will most likely not exist in the Pro version. VIA is extremely specific in the roadmap to not mention that their PEG solution is x16. It may be the case that we see two x8 devices with x16 interconnects. This is perfectly allowable int the PCIe specification; Intel implements it just so in their Tumwater chipset.

Below you can see VIA's approach to the PT894 Pro chipset. Notice the lack of additional PCIe devices stemming from the northbridge.

The PT894 Pro and K8T890 Pro both look to only utilize the new VT8251 southbridge. We have lightly talked about this southbridge in the past but never had many details to report on it. It looks to us the VT8251 will differ from the tried and true VT8237 in two ways; new 8 channel audio support and native NCQ for SATA. Look forward to seeing VT8251 on reference motherboards sometime before September.

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  • jaisriramin - Tuesday, June 28, 2005 - link

    Hi everyone,
    i have just started working on PCI-Express
    and don't kow much about it. could anyone please clear some of my doubts?

    1> I want to find nunmber of lanes of any given PCI-Express. Is it the value in Link status register?

    2> How do i access this value? Will i need to write any driver for accessing the register? I am working on VC++ platform.

  • AlecRyben - Tuesday, August 24, 2004 - link

    If you put two X16 PCI-E slots on a motherboard, does that mean that you cannot have any other PCI-E slots? Is 32 lanes the maximum you can use?
    If that's the case, i see no point in having that. I would rather have two X8 slots and leave the remaining 16 lanes available for additional expansion (for 1X/2X/4X capable slots for example)
  • KristopherKubicki - Monday, August 23, 2004 - link

    cheburashka: You can use x10 for power but only x8 for moving data. I will change my wording a little.

  • jagd - Friday, August 20, 2004 - link

    via had pllanning 4 pieces 4x pci ekspress slot ,probably they made 1 piece 16 pci-ekspress slotthanks for scalable pci ekspress artitecture
  • thebluesgnr - Thursday, August 19, 2004 - link

    The lack of native Gigabit in the new southbridge is a little disappointing, but I assume it won't be a problem if it's attached to the PCIe bus.
  • cheburashka - Thursday, August 19, 2004 - link

    I have been working with PCIe for over two years now and designed the Transaction Layer used in Intel's internal validation card. I am certain I know what I am talking about.

    From the 1.0a spec Link Status Register:
    Negotiated Link Width – This field indicates the negotiated width of the given PCI Express Link.
    Defined encodings are:
    000001b X1
    000010b X2
    000100b X4
    001000b X8
    001100b X12
    010000b X16
    100000b X32
    All other encodings are reserved.
  • KristopherKubicki - Wednesday, August 18, 2004 - link

    cheburashka, 10 lanes on a x16 interface?

  • cheburashka - Tuesday, August 17, 2004 - link

    This guy is wrong, x10 is not allowed by the PCIe spec.
  • klah - Monday, August 16, 2004 - link

    I doubt that NV will launch SLI before NF4, forcing people to buy VIA boards to use it. I am sure they want to get SLI/NF4 launched before xmas.
  • danidentity - Sunday, August 15, 2004 - link

    >>Now where is NF4 and Pci-e???

    Heh, no kidding. :)

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